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  • Latchup prevention by using guard ring structures in a 0.8 µm bulk CMOS process
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Latchup prevention by using guard ring structures in a 0.8 µm bulk CMOS process

Fuente: Redalyc
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Bibliographic Details
Main Author: Felipe Coyotl
Format: Artículo científico
Language:en
Published: Sociedad Mexicana de Ciencia y Tecnología de Superficies y Materiales A.C. 2004
Subjects:
Física, Astronomía y Matemáticas
Latchup
Avalanching
Punchthrough
Guard ring structures
Online Access:
Acceder al recurso
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Internet

https://www.redalyc.org/articulo.oa?id=94217405

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