A Low‐Complexity Digital Predistortion Technology and FPGA Implementation for Wide‐Band Satellite Communication
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Wiley
2025
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| author | Mingchen Jiang Mingyu Li Zhiyuan Zhao Huijian Liang Xin Luo Shuman Kong Tianfu Cai |
| author_facet | Mingchen Jiang Mingyu Li Zhiyuan Zhao Huijian Liang Xin Luo Shuman Kong Tianfu Cai Mingchen Jiang Mingyu Li Zhiyuan Zhao Huijian Liang Xin Luo Shuman Kong Tianfu Cai |
| collection | Wiley Open Access |
| contents | A Low‐Complexity Digital Predistortion Technology and FPGA Implementation for Wide‐Band Satellite Communication Mingchen Jiang Mingyu Li Zhiyuan Zhao Huijian Liang Xin Luo Shuman Kong Tianfu Cai International Journal of Circuit Theory and Applications ABSTRACT In this paper, a low‐complexity digital predistortion (DPD) technique is proposed to compensate for the joint nonlinear distortions, such as the nonlinearity of power amplifier (PA), I/Q imbalance, and the filter group delay in broadband satellite communication system links. The proposed DPD technique is based on a band‐limited IQ‐separated memory polynomial (BL‐IQMP) model and a parallel lookup table (LUT) architecture. The proposed model separates the real and imaginary parts of the polynomial kernel to counteract the effect of I/Q imbalance. For band‐limited systems, the modeling bandwidth is controlled by introducing a band‐limit function. In addition, a smooth twins support vector regression (STSVR) method is used instead of the traditional least squares (LS) method in the parameter‐solving process to increase the accuracy of the modeling. The proposed architecture utilizes parallel signal processing techniques to circumvent the hardware clock frequency limitation, concurrently employing the LUT method to minimize hardware resource consumption substantially. Subsequently, the DPD experiments are conducted with 625‐MHz 16 and 32APSK signals on the traveling‐wave tube amplifier (TWTA) in the Ka‐band, respectively. The experimental findings demonstrate that the proposed predistortion scheme has the capacity to substantially reduce the EVM of the signals and circumvent the loss of lock of phase‐locked loop (PLL). This provides an effective solution for the predistortion technique employed in the radio frequency (RF) front‐end of satellite communication systems. 10.1002/cta.70002 http://onlinelibrary.wiley.com/termsAndConditions#vor |
| doi_str_mv | 10.1002/cta.70002 |
| format | Artículo Open Access |
| id | wiley_oa_10_1002_cta_70002 |
| institution | Wiley Open Access |
| license_str_mv | http://onlinelibrary.wiley.com/termsAndConditions#vor |
| publishDate | 2025 |
| publisher | Wiley |
| record_format | wiley_oa |
| spellingShingle | A Low‐Complexity Digital Predistortion Technology and FPGA Implementation for Wide‐Band Satellite Communication Mingchen Jiang Mingyu Li Zhiyuan Zhao Huijian Liang Xin Luo Shuman Kong Tianfu Cai International Journal of Circuit Theory and Applications A Low‐Complexity Digital Predistortion Technology and FPGA Implementation for Wide‐Band Satellite Communication Mingchen Jiang Mingyu Li Zhiyuan Zhao Huijian Liang Xin Luo Shuman Kong Tianfu Cai International Journal of Circuit Theory and Applications ABSTRACT In this paper, a low‐complexity digital predistortion (DPD) technique is proposed to compensate for the joint nonlinear distortions, such as the nonlinearity of power amplifier (PA), I/Q imbalance, and the filter group delay in broadband satellite communication system links. The proposed DPD technique is based on a band‐limited IQ‐separated memory polynomial (BL‐IQMP) model and a parallel lookup table (LUT) architecture. The proposed model separates the real and imaginary parts of the polynomial kernel to counteract the effect of I/Q imbalance. For band‐limited systems, the modeling bandwidth is controlled by introducing a band‐limit function. In addition, a smooth twins support vector regression (STSVR) method is used instead of the traditional least squares (LS) method in the parameter‐solving process to increase the accuracy of the modeling. The proposed architecture utilizes parallel signal processing techniques to circumvent the hardware clock frequency limitation, concurrently employing the LUT method to minimize hardware resource consumption substantially. Subsequently, the DPD experiments are conducted with 625‐MHz 16 and 32APSK signals on the traveling‐wave tube amplifier (TWTA) in the Ka‐band, respectively. The experimental findings demonstrate that the proposed predistortion scheme has the capacity to substantially reduce the EVM of the signals and circumvent the loss of lock of phase‐locked loop (PLL). This provides an effective solution for the predistortion technique employed in the radio frequency (RF) front‐end of satellite communication systems. 10.1002/cta.70002 http://onlinelibrary.wiley.com/termsAndConditions#vor |
| title | A Low‐Complexity Digital Predistortion Technology and FPGA Implementation for Wide‐Band Satellite Communication |
| topic | International Journal of Circuit Theory and Applications |
| url | https://onlinelibrary.wiley.com/doi/10.1002/cta.70002 |