Design and Analysis of ΔΣ Modulator Analogous Bang‐Bang Digital PLL
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2025
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| _version_ | 1867013194581540864 |
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| author | Minsu Park Jong‐Hyeok Yoon Minyoung Song |
| author_facet | Minsu Park Jong‐Hyeok Yoon Minyoung Song Minsu Park Jong‐Hyeok Yoon Minyoung Song |
| collection | Wiley Open Access |
| contents | Design and Analysis of ΔΣ Modulator Analogous Bang‐Bang Digital PLL Minsu Park Jong‐Hyeok Yoon Minyoung Song International Journal of Circuit Theory and Applications ABSTRACT This paper presents the analysis and design methodology of a second‐order ΔΣ modulator analogous bang‐bang digital phase‐locked loop (DSBPLL). When the bang‐bang‐based digital PLL (BB‐DPLL) cannot fully track the DCO jitter, the jitter slewing effect exacerbates the in‐band noise. The proposed DSBPLL can increase the PLL filter order without using a high‐order loop filter, thereby mitigating the in‐band noise caused by input tracking jitter. Theoretical noise analysis confirmed that the proposed DSBPLL can reduce 54.3% of the integrated jitter from 100 kHz to 100 MHz, consistent with the measurement results. 10.1002/cta.70013 http://onlinelibrary.wiley.com/termsAndConditions#vor |
| doi_str_mv | 10.1002/cta.70013 |
| format | Artículo Open Access |
| id | wiley_oa_10_1002_cta_70013 |
| institution | Wiley Open Access |
| license_str_mv | http://onlinelibrary.wiley.com/termsAndConditions#vor |
| publishDate | 2025 |
| publisher | Wiley |
| record_format | wiley_oa |
| spellingShingle | Design and Analysis of ΔΣ Modulator Analogous Bang‐Bang Digital PLL Minsu Park Jong‐Hyeok Yoon Minyoung Song International Journal of Circuit Theory and Applications Design and Analysis of ΔΣ Modulator Analogous Bang‐Bang Digital PLL Minsu Park Jong‐Hyeok Yoon Minyoung Song International Journal of Circuit Theory and Applications ABSTRACT This paper presents the analysis and design methodology of a second‐order ΔΣ modulator analogous bang‐bang digital phase‐locked loop (DSBPLL). When the bang‐bang‐based digital PLL (BB‐DPLL) cannot fully track the DCO jitter, the jitter slewing effect exacerbates the in‐band noise. The proposed DSBPLL can increase the PLL filter order without using a high‐order loop filter, thereby mitigating the in‐band noise caused by input tracking jitter. Theoretical noise analysis confirmed that the proposed DSBPLL can reduce 54.3% of the integrated jitter from 100 kHz to 100 MHz, consistent with the measurement results. 10.1002/cta.70013 http://onlinelibrary.wiley.com/termsAndConditions#vor |
| title | Design and Analysis of ΔΣ Modulator Analogous Bang‐Bang Digital PLL |
| topic | International Journal of Circuit Theory and Applications |
| url | https://onlinelibrary.wiley.com/doi/10.1002/cta.70013 |