Using Boolean Algebra to Minimize the LUT Count for FPGA Implementation of BCD Adders

Fuente: Wiley Open Access

Saved in:

Bibliographic Details
Main Author:	Supriya Aggarwal
Format:	Artículo Open Access
Published:	Wiley 2026
Subjects:	International Journal of Circuit Theory and Applications
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Description
DOI:	10.1002/cta.70366

Similar Items