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| Main Authors: | , , , , , , , , , |
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| Format: | Artículo Open Access |
| Published: |
Wiley
2026
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| Subjects: | |
| Online Access: | https://onlinelibrary.wiley.com/doi/10.1002/mop.70521 |
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Table of Contents:
- Ultra Low Jitter Wideband Frequency Synthesizer With Gain‐Enhanced PFD Yanhui Wu Shize Duan Zhenrong Li Hua Xu Qiong Li Jie Li Tao Zhang Bo Yuan Tianyu Deng Cong Li Microwave and Optical Technology Letters ABSTRACT In this paper, we present a frequency synthesizer based on fractional‐N CP‐PLL architecture to achieve continuous frequency coverage from 6 to 24 GHz. To address the problem of modulator folded quantization noise deteriorating the phase noise performance of the PLL, a gain‐enhanced PFD is proposed to improve the CP charge pump linearity. The chip is fabricated in a 0.18‐m SiGe BiCMOS process and the measurement results show that the phase noise from 12.01 GHz carrier is −110.9 dBc/Hz at 100 kHz offset, which is a 26 dB decrease in the in‐band phase noise compared to that when using a conventional PFD. With the gain‐enhanced PFD optimizing phase noise, an RMS jitter of 77.6 fs (integrated from 12 kHz to 20 MHz) and a reference spur of −69.6 dBc at the 12.01 GHz carrier are achieved. The chip operates on an 3.3 V supply with a DC power consumption of 528 mW. 10.1002/mop.70521 http://onlinelibrary.wiley.com/termsAndConditions#vor