Hardware efficient multiplier design for deep learning processing unit

Fuente: Zenodo

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Bibliographic Details
Main Authors:	Jean Shilpa V., Anitha R., Anusooya S., Jawahar P. K., Nithesh E., Sairamsiva S., Syed Rahaman K.
Format:	Recurso digital
Published:	Zenodo 2025
Subjects:	Booth multiplier Deep learning processing unit Field programmable gate array Pipeline Po2 multiplier
Online Access:	Acceder al recurso
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