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Zenodo
2025
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| Online Access: | https://doi.org/10.5281/zenodo.15093784 |
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| author | A Raja SK A Abraham Likitha V P Harikrishna V Ganesh |
| author_facet | A Raja SK A Abraham Likitha V P Harikrishna V Ganesh |
| contents | <p><em><span>Efficient summation of multiple operands in parallel is a crucial aspect of digital signal processing (DSP) systems. To enhance performance, high-compression-ratio counters and compressors play a vital role in accelerating the summation process. In this work, we propose a novel approach for designing fast saturated binary counters and exact/approximate (4:2) compressors utilizing sorting networks. The counter inputs are asymmetrically divided into two groups and processed through sorting networks, generating reordered sequences that can be efficiently represented using one-hot encoding. Three specialized Boolean equations are formulated to establish a direct relationship between the reordered sequence and the one-hot code, significantly simplifying the output logic of the counter. Using this methodology, we design and optimize a (7,3) counter that outperforms existing designs in terms of delay, area-delay product, and power-delay product. The proposed design is implemented using Verilog HDL, with simulation and synthesis performed on the Xilinx ISE tool, demonstrating its effectiveness in improving computational efficiency.</span></em></p> |
| format | Recurso digital |
| id | zenodo_https___doi_org_10_5281_zenodo_15093784 |
| institution | Zenodo |
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| publishDate | 2025 |
| publisher | Zenodo |
| record_format | zenodo |
| spellingShingle | Optimized Saturated Binary Counters and (4:2) Compressors Using Sorting Networks for High-Speed Summation A Raja SK A Abraham Likitha V P Harikrishna V Ganesh <p><em><span>Efficient summation of multiple operands in parallel is a crucial aspect of digital signal processing (DSP) systems. To enhance performance, high-compression-ratio counters and compressors play a vital role in accelerating the summation process. In this work, we propose a novel approach for designing fast saturated binary counters and exact/approximate (4:2) compressors utilizing sorting networks. The counter inputs are asymmetrically divided into two groups and processed through sorting networks, generating reordered sequences that can be efficiently represented using one-hot encoding. Three specialized Boolean equations are formulated to establish a direct relationship between the reordered sequence and the one-hot code, significantly simplifying the output logic of the counter. Using this methodology, we design and optimize a (7,3) counter that outperforms existing designs in terms of delay, area-delay product, and power-delay product. The proposed design is implemented using Verilog HDL, with simulation and synthesis performed on the Xilinx ISE tool, demonstrating its effectiveness in improving computational efficiency.</span></em></p> |
| title | Optimized Saturated Binary Counters and (4:2) Compressors Using Sorting Networks for High-Speed Summation |
| url | https://doi.org/10.5281/zenodo.15093784 |