Digital Sign Calculator Verification and Implementation of Verilog HDL via FPGA Simulation
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| Natura: | Recurso digital |
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Zenodo
2025
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| _version_ | 1866902325363212288 |
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| author | IJMSRT |
| author_facet | IJMSRT |
| contents | <p>It is a possible to set up a digital sign calculator <br>in the course of daily living. In this exploration <br>composition, the pattern of a sign calculator is <br>brought forward by using a format of Verilog <br>HDL. Much synthetic Verilog code was created <br>and obtained in Artix-7. The design of a 9-bit <br>digital <br>sign calculator can break fine <br>mathematical operations similar to adder, <br>subtract, multiplier, and divider. This digital <br>sign calculator consists of nine-digit figures. <br>The simulation procedure will be carried out in <br>this article using devices from the Xilinx <br>family. A shaft-style simulation of the <br>calculator design is one of the outputs <br>displayed in the waveform and RTL view. <br>Calculator facts have been used favorably using <br>Verilog HDL in relation to the behavior of the <br>sign calculator functions.</p> |
| format | Recurso digital |
| id | zenodo_https___doi_org_10_5281_zenodo_15273110 |
| institution | Zenodo |
| language | |
| publishDate | 2025 |
| publisher | Zenodo |
| record_format | zenodo |
| spellingShingle | Digital Sign Calculator Verification and Implementation of Verilog HDL via FPGA Simulation IJMSRT <p>It is a possible to set up a digital sign calculator <br>in the course of daily living. In this exploration <br>composition, the pattern of a sign calculator is <br>brought forward by using a format of Verilog <br>HDL. Much synthetic Verilog code was created <br>and obtained in Artix-7. The design of a 9-bit <br>digital <br>sign calculator can break fine <br>mathematical operations similar to adder, <br>subtract, multiplier, and divider. This digital <br>sign calculator consists of nine-digit figures. <br>The simulation procedure will be carried out in <br>this article using devices from the Xilinx <br>family. A shaft-style simulation of the <br>calculator design is one of the outputs <br>displayed in the waveform and RTL view. <br>Calculator facts have been used favorably using <br>Verilog HDL in relation to the behavior of the <br>sign calculator functions.</p> |
| title | Digital Sign Calculator Verification and Implementation of Verilog HDL via FPGA Simulation |
| url | https://doi.org/10.5281/zenodo.15273110 |