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| Main Authors: | , |
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| Format: | Recurso digital |
| Language: | |
| Published: |
Zenodo
2025
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| Online Access: | https://doi.org/10.5281/zenodo.15280657 |
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Table of Contents:
- This repository contains two implementations of a phase-locked loop (PLL) on a FPGA (field-programmable gate array). We use the Labview graphical programming environment to generate FPGA binary code and a PC interface.