Saved in:
| Main Authors: | , , , , |
|---|---|
| Format: | Recurso digital |
| Language: | |
| Published: |
Zenodo
2024
|
| Subjects: | |
| Online Access: | https://doi.org/10.5281/zenodo.15455573 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| _version_ | 1866902189634486272 |
|---|---|
| author | Rajapriyadharshini, B Renisha, V Shivani, S Bharath Kumar, S Latha, P |
| author_facet | Rajapriyadharshini, B Renisha, V Shivani, S Bharath Kumar, S Latha, P |
| contents | <p><span lang="EN-US">This paper presents the design and implementation of an analog integrated circuit (IC) based on the Wilson current mirror topology. The design process was carried out using the Cadence Virtuoso tool suite. The initial phase involved creating the schematic in the Schematic Editor and generating a corresponding symbol to represent the circuit. A test bench was subsequently constructed using this symbol to enable simulation and performance evaluation. Input and output waveforms were obtained and analyzed to validate the functionality of the design. Additionally, the layout was generated and modified to meet design specifications. Physical verification, including Design Rule Check (DRC), Layout Versus Schematic (LVS), and RC extraction, was conducted using the Assura tool to ensure compliance<span> </span>with<span> </span>design<span> </span>rules.<span> </span>Finally,<span> </span>the<span> </span>design<span> </span>was<span> </span>prepared<span> </span>for<span> </span>fabrication<span> </span>through<span> </span>the<span> </span>generation<span> </span>of a Graphic Design System (GDS) file.</span></p> |
| format | Recurso digital |
| id | zenodo_https___doi_org_10_5281_zenodo_15455573 |
| institution | Zenodo |
| language | |
| publishDate | 2024 |
| publisher | Zenodo |
| record_format | zenodo |
| spellingShingle | Analog / Full Custom IC Design of Wilson Current Mirror Rajapriyadharshini, B Renisha, V Shivani, S Bharath Kumar, S Latha, P Integrated Circuit (IC); Design Rule Check (DRC); Layout Versus Schematic (LVS); Resistance- Capacitance (RC); Graphic Design System (GDS); Metal Oxide Semiconductor (MOS); Assura Verification (AV) <p><span lang="EN-US">This paper presents the design and implementation of an analog integrated circuit (IC) based on the Wilson current mirror topology. The design process was carried out using the Cadence Virtuoso tool suite. The initial phase involved creating the schematic in the Schematic Editor and generating a corresponding symbol to represent the circuit. A test bench was subsequently constructed using this symbol to enable simulation and performance evaluation. Input and output waveforms were obtained and analyzed to validate the functionality of the design. Additionally, the layout was generated and modified to meet design specifications. Physical verification, including Design Rule Check (DRC), Layout Versus Schematic (LVS), and RC extraction, was conducted using the Assura tool to ensure compliance<span> </span>with<span> </span>design<span> </span>rules.<span> </span>Finally,<span> </span>the<span> </span>design<span> </span>was<span> </span>prepared<span> </span>for<span> </span>fabrication<span> </span>through<span> </span>the<span> </span>generation<span> </span>of a Graphic Design System (GDS) file.</span></p> |
| title | Analog / Full Custom IC Design of Wilson Current Mirror |
| topic | Integrated Circuit (IC); Design Rule Check (DRC); Layout Versus Schematic (LVS); Resistance- Capacitance (RC); Graphic Design System (GDS); Metal Oxide Semiconductor (MOS); Assura Verification (AV) |
| url | https://doi.org/10.5281/zenodo.15455573 |