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Bibliographic Details
Main Authors:	Rajapriyadharshini, B, Renisha, V, Shivani, S, Bharath Kumar, S, Latha, P
Format:	Recurso digital
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Published:	Zenodo 2024
Subjects:	Integrated Circuit (IC); Design Rule Check (DRC); Layout Versus Schematic (LVS); Resistance- Capacitance (RC); Graphic Design System (GDS); Metal Oxide Semiconductor (MOS); Assura Verification (AV)
Online Access:	https://doi.org/10.5281/zenodo.15455573
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