Design and Optimization of a Wallace Tree Multiplier Using Han-Carlson Adder for High-Performance Arithmetic Units
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| Formato: | Recurso digital |
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2025
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| _version_ | 1866902103677468672 |
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| author | Kaipu Chandrika Dr. M Apparao |
| author_facet | Kaipu Chandrika Dr. M Apparao |
| contents | <p><em><span lang="EN-US">High-speed multiplication is a critical operation in digital signal processing, cryptography, and scientific computing. Wallace Tree multipliers are widely known for their efficient partial product reduction using parallel compressor logic. However, the final addition stage significantly impacts the overall performance of the multiplier. In this work, we propose a performance-enhanced 16-bit Wallace Tree multiplier architecture by replacing the conventional Brent-Kung Adder with a Han-Carlson Adder for the final summation. The Han-Carlson adder provides a balanced trade-off between logic depth and wiring complexity, thereby reducing delay while maintaining area efficiency. A comparative analysis was conducted using Verilog HDL and synthesized on an FPGA platform. Results demonstrate that the proposed architecture achieves lower propagation delay with competitive area usage, making it suitable for real-time arithmetic-intensive applications.<span> </span></span></em></p> |
| format | Recurso digital |
| id | zenodo_https___doi_org_10_5281_zenodo_16153785 |
| institution | Zenodo |
| language | |
| publishDate | 2025 |
| publisher | Zenodo |
| record_format | zenodo |
| spellingShingle | Design and Optimization of a Wallace Tree Multiplier Using Han-Carlson Adder for High-Performance Arithmetic Units Kaipu Chandrika Dr. M Apparao <p><em><span lang="EN-US">High-speed multiplication is a critical operation in digital signal processing, cryptography, and scientific computing. Wallace Tree multipliers are widely known for their efficient partial product reduction using parallel compressor logic. However, the final addition stage significantly impacts the overall performance of the multiplier. In this work, we propose a performance-enhanced 16-bit Wallace Tree multiplier architecture by replacing the conventional Brent-Kung Adder with a Han-Carlson Adder for the final summation. The Han-Carlson adder provides a balanced trade-off between logic depth and wiring complexity, thereby reducing delay while maintaining area efficiency. A comparative analysis was conducted using Verilog HDL and synthesized on an FPGA platform. Results demonstrate that the proposed architecture achieves lower propagation delay with competitive area usage, making it suitable for real-time arithmetic-intensive applications.<span> </span></span></em></p> |
| title | Design and Optimization of a Wallace Tree Multiplier Using Han-Carlson Adder for High-Performance Arithmetic Units |
| url | https://doi.org/10.5281/zenodo.16153785 |