APA (7th ed.) Citation

Sravya, G., & Anjaneyulu, K. (2025). Design and Implementation of a 32-bit Carry Lookahead Adder (CLA) in Verilog. Zenodo.

Chicago Style (17th ed.) Citation

Sravya, G., and K. Anjaneyulu. Design and Implementation of a 32-bit Carry Lookahead Adder (CLA) in Verilog. Zenodo, 2025.

MLA (9th ed.) Citation

Sravya, G., and K. Anjaneyulu. Design and Implementation of a 32-bit Carry Lookahead Adder (CLA) in Verilog. Zenodo, 2025.

Warning: These citations may not always be 100% accurate.