Cover Image

Titan-I: An Open-Source High Performance RISC-V Vector Core

Fuente: Zenodo

Saved in:

Bibliographic Details
Main Author:	Liu, Jiuyang
Format:	Recurso digital
Published:	Zenodo 2025
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

A "New Ara" for Vector Computing: An Open Source Highly Efficient RISC-V V 1.0 Vector Processor Design
by: Perotti, Matteo, et al.
Published: (2022)

Not All Faults Are Equal: Transient-Fault Sensitivity Characterization of an Open-Source RISC-V Vector Cluster
by: Cai, Maoyuan, et al.
Published: (2026)

Research on LLM Acceleration Using the High-Performance RISC-V Processor "Xiangshan" (Nanhu Version) Based on the Open-Source Matrix Instruction Set Extension (Vector Dot Product)
by: Chen, Xu-Hao, et al.
Published: (2024)

Vitamin-V: Expanding Open-Source RISC-V Cloud Environments
by: Canal, Ramon, et al.
Published: (2024)

basic_RV32s: An Open-Source Microarchitectural Roadmap for RISC-V RV32I
by: Kang, Hyun Woo, et al.
Published: (2025)

Closer in the Gap: Towards Portable Performance on RISC-V Vector Processors
by: Shi, Ruimin, et al.
Published: (2026)

Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution
by: Fu, Zexin, et al.
Published: (2025)

Basilisk: Achieving Competitive Performance with Open EDA Tools on an Open-Source Linux-Capable RISC-V SoC
by: Sauter, Phillippe, et al.
Published: (2024)

Work-In-Progress: Accelerating Numpy With OpenBLAS For Open-Source RISC-V Chips
by: Koenig, Cyril, et al.
Published: (2025)

Spatzformer: An Efficient Reconfigurable Dual-Core RISC-V V Cluster for Mixed Scalar-Vector Workloads
by: Perotti, Matteo, et al.
Published: (2024)

Synthesis of Sound and Precise Leakage Contracts for Open-Source RISC-V Processors
by: Wang, Zilong, et al.
Published: (2025)

Synthesizing Hardware-Software Leakage Contracts for RISC-V Open-Source Processors
by: Mohr, Gideon, et al.
Published: (2024)

Support Vector Machines Classification on Bendable RISC-V
by: Vergos, Polykarpos, et al.
Published: (2025)

Efficient Architecture for RISC-V Vector Memory Access
by: Guan, Hongyi, et al.
Published: (2025)

Efficient Implementation of RISC-V Vector Permutation Instructions
by: Titopoulos, Vasileios, et al.
Published: (2025)

Pedagogically Motivated and Composable Open-Source RISC-V Processors for Computer Science Education
by: McDougall, Ian, et al.
Published: (2025)

Physical Design of UET-RVMCU: A Streamlined Open-Source RISC-V Microcontroller
by: Azhar, Abdullah, et al.
Published: (2026)

Preparing for HPC on RISC-V: Examining Vectorization and Distributed Performance of an Astrophyiscs Application with HPX and Kokkos
by: Diehl, Patrick, et al.
Published: (2024)

X-HEEP: An Open-Source, Configurable and Extendible RISC-V Platform for TinyAI Applications
by: Machetti, Simone, et al.
Published: (2025)

Croc: An End-to-End Open-Source Extensible RISC-V MCU Platform to Democratize Silicon
by: Sauter, Phillippe, et al.
Published: (2025)

EARTH: Efficient Architecture for RISC-V Vector Memory Access
by: Guan, Hongyi, et al.
Published: (2025)

Implementing and Optimizing an Open-Source SD-card Host Controller for RISC-V SoCs
by: Vanoni, Axel, et al.
Published: (2026)

Vectorized FlashAttention with Low-cost Exponential Computation in RISC-V Vector Processors
by: Titopoulos, Vasileios, et al.
Published: (2025)

CryptRISC: A Secure RISC-V Processor for High-Performance Cryptography with Power Side-Channel Protection
by: Srivastava, Amisha, et al.
Published: (2026)

RISC-V V Vector Extension (RVV) with reduced number of vector registers
by: Jacobs, Eino, et al.
Published: (2024)

Runtime Energy Monitoring for RISC-V Soft-Cores
by: Scionti, Alberto, et al.
Published: (2025)

Optimizing Energy Efficiency in Subthreshold RISC-V Cores
by: Djupdal, Asbjørn, et al.
Published: (2025)

HERMES: High-Performance RISC-V Memory Hierarchy for ML Workloads
by: Suryadevara, Pranav
Published: (2025)

e-GPU: An Open-Source and Configurable RISC-V Graphic Processing Unit for TinyAI Applications
by: Machetti, Simone, et al.
Published: (2025)

NoX: a Compact Open-Source RISC-V Processor for Multi-Processor Systems-on-Chip
by: Silva, Anderson I., et al.
Published: (2024)

Unlimited Vector Processing for Wireless Baseband Based on RISC-V Extension
by: Jiang, Limin, et al.
Published: (2025)

Optimizing Structured-Sparse Matrix Multiplication in RISC-V Vector Processors
by: Titopoulos, Vasileios, et al.
Published: (2025)

CVA6S+: A Superscalar RISC-V Core with High-Throughput Memory Architecture
by: Tedeschi, Riccardo, et al.
Published: (2025)

PermuteV: A Performant Side-channel-Resistant RISC-V Core Securing Edge AI Inference
by: Narkthong, Nuntipat, et al.
Published: (2025)

Is RISC-V ready for High Performance Computing? An evaluation of the Sophon SG2044
by: Brown, Nick
Published: (2025)

Taming Offload Overheads in a Massively Parallel Open-Source RISC-V MPSoC: Analysis and Optimization
by: Colagrande, Luca, et al.
Published: (2025)

Basilisk: An End-to-End Open-Source Linux-Capable RISC-V SoC in 130nm CMOS
by: Scheffler, Paul, et al.
Published: (2024)

Culsans: An Efficient Snoop-based Coherency Unit for the CVA6 Open Source RISC-V application processor
by: Tedeschi, Riccardo, et al.
Published: (2024)

Tensor Program Optimization for the RISC-V Vector Extension Using Probabilistic Programs
by: Peccia, Federico Nicolas, et al.
Published: (2025)

IntrinTrans: LLM-based Intrinsic Code Translator for RISC-V Vector
by: Han, Liutong, et al.
Published: (2025)