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| Main Authors: | , , |
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| Format: | Recurso digital |
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Zenodo
2025
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| Online Access: | https://doi.org/10.5281/zenodo.17006229 |
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Table of Contents:
- <p>This repository contains the code for the paper "EARTH: Efficient Architecture for RISC-V Vector Memory Access".</p> <p>- A processor supports the entire RVV 1.0, based on [saturn-vector](https://github.com/ucb-bar/saturn-vectors)<br>- VLEN & DLEN = 512 bits<br>- Enhance VLSU with Shift Network:<br> - Unit-Stride<br> - Strided<br> - Unit-Stride Segment<br> - Strided Segment</p>