INTEGRATION OF LLVM AND ICARUS VERILOG FOR THE COMPILATION AND SIMULATION OF CUSTOM PROCESSORS.
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| Format: | Recurso digital |
| Language: | Portuguese |
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Zenodo
2025
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| _version_ | 1866901196896206848 |
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| author | Silva, Murillo Inácio da Costa Pereira, Icaro Mayan Lima Silva, Danilo Lacerda Nepomuceno, Ramon Santos |
| author_facet | Silva, Murillo Inácio da Costa Pereira, Icaro Mayan Lima Silva, Danilo Lacerda Nepomuceno, Ramon Santos |
| contents | <p><span lang="PT">This paper presents a methodology for the integration of LLVM and Icarus Verilog, aiming at the compilation and simulation of custom processors. The combination of these two technologies provides an efficient workflow, from hardware description to executable code generation. The research involved extensive research and practical steps to enable LLVM to recognize the Cpu0 educational processor as a valid target, including cloning and building LLVM with specific Cpu0 support.<a name="_28f8je5rhygx"></a> The work details the process of generating assembly code for the Cpu0 architecture from a C++ program and converting it to a hexadecimal format readable by Verilog. Furthermore, the study explored the adaptation of the Cpu0 architecture by demonstrating how to successfully remove a register and an instruction, showcasing the flexibility of the LLVM backend. This methodology provides a practical and accessible approach for developers and researchers, filling the gap of didactic sources on the subject. The results highlight the potential for this integration to streamline the workflow for developing application-specific processors.</span></p> |
| format | Recurso digital |
| id | zenodo_https___doi_org_10_5281_zenodo_17415147 |
| institution | Zenodo |
| language | por |
| publishDate | 2025 |
| publisher | Zenodo |
| record_format | zenodo |
| spellingShingle | INTEGRATION OF LLVM AND ICARUS VERILOG FOR THE COMPILATION AND SIMULATION OF CUSTOM PROCESSORS. Silva, Murillo Inácio da Costa Pereira, Icaro Mayan Lima Silva, Danilo Lacerda Nepomuceno, Ramon Santos Compilation; LLVM; Simulation; Processors; Verilog <p><span lang="PT">This paper presents a methodology for the integration of LLVM and Icarus Verilog, aiming at the compilation and simulation of custom processors. The combination of these two technologies provides an efficient workflow, from hardware description to executable code generation. The research involved extensive research and practical steps to enable LLVM to recognize the Cpu0 educational processor as a valid target, including cloning and building LLVM with specific Cpu0 support.<a name="_28f8je5rhygx"></a> The work details the process of generating assembly code for the Cpu0 architecture from a C++ program and converting it to a hexadecimal format readable by Verilog. Furthermore, the study explored the adaptation of the Cpu0 architecture by demonstrating how to successfully remove a register and an instruction, showcasing the flexibility of the LLVM backend. This methodology provides a practical and accessible approach for developers and researchers, filling the gap of didactic sources on the subject. The results highlight the potential for this integration to streamline the workflow for developing application-specific processors.</span></p> |
| title | INTEGRATION OF LLVM AND ICARUS VERILOG FOR THE COMPILATION AND SIMULATION OF CUSTOM PROCESSORS. |
| topic | Compilation; LLVM; Simulation; Processors; Verilog |
| url | https://doi.org/10.5281/zenodo.17415147 |