AI based SystemVerilog TB generation

Fuente: Zenodo

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Bibliographic Details
Main Author:	Bhavin Shah
Format:	Recurso digital
Published:	Zenodo 2017
Subjects:	Artificial Intelligence SystemVerilog Testbench Generation Functional Verification Universal Verification Methodology (UVM) Machine Learning Static Analysis ASIC Design Coverage Closure
Online Access:	Acceder al recurso
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