AI based SystemVerilog TB generation
Fuente:
Zenodo
Salvato in:
| Autore principale: | |
|---|---|
| Natura: | Recurso digital |
| Pubblicazione: |
Zenodo
2017
|
| Soggetti: | |
| Accesso online: | |
| Tags: |
Aggiungi Tag
Nessun Tag, puoi essere il primo ad aggiungerne!!
|
| _version_ | 1866901240852512768 |
|---|---|
| author | Bhavin Shah |
| author_facet | Bhavin Shah |
| contents | <p><span lang="EN-US">As the complexity of Application-Specific Integrated Circuit (ASIC) designs continues to escalate, functional verification has emerged as the most resource-intensive phase, consuming a substantial portion of the overall development effort. Traditional verification approaches, reliant on manually created SystemVerilog testbenches, are increasingly challenged to provide adequate coverage in a reasonable timeframe. This paper explores methodologies for automating verification testbenches using artificial intelligence techniques that predate modern large language models. A key area of investigation is the integration of static code analysis to identify critical verification areas and map dependencies between design inputs and internal state variables. Building on this analysis, the discussion examines how machine learning models can be trained on design specifications to automatically generate targeted test stimuli and verification components. The focus is on how such a data-driven approach can shift verification from a reactive to a more proactive process, potentially allowing for earlier bug detection and faster coverage closure. The overall objective is to examine how these AI-based techniques can reduce the manual effort in testbench creation and enhance the efficiency of the ASIC verification cycle.</span></p> |
| format | Recurso digital |
| id | zenodo_https___doi_org_10_5281_zenodo_17587919 |
| institution | Zenodo |
| language | |
| publishDate | 2017 |
| publisher | Zenodo |
| record_format | zenodo |
| spellingShingle | AI based SystemVerilog TB generation Bhavin Shah Artificial Intelligence SystemVerilog Testbench Generation Functional Verification Universal Verification Methodology (UVM) Machine Learning Static Analysis ASIC Design Coverage Closure <p><span lang="EN-US">As the complexity of Application-Specific Integrated Circuit (ASIC) designs continues to escalate, functional verification has emerged as the most resource-intensive phase, consuming a substantial portion of the overall development effort. Traditional verification approaches, reliant on manually created SystemVerilog testbenches, are increasingly challenged to provide adequate coverage in a reasonable timeframe. This paper explores methodologies for automating verification testbenches using artificial intelligence techniques that predate modern large language models. A key area of investigation is the integration of static code analysis to identify critical verification areas and map dependencies between design inputs and internal state variables. Building on this analysis, the discussion examines how machine learning models can be trained on design specifications to automatically generate targeted test stimuli and verification components. The focus is on how such a data-driven approach can shift verification from a reactive to a more proactive process, potentially allowing for earlier bug detection and faster coverage closure. The overall objective is to examine how these AI-based techniques can reduce the manual effort in testbench creation and enhance the efficiency of the ASIC verification cycle.</span></p> |
| title | AI based SystemVerilog TB generation |
| topic | Artificial Intelligence SystemVerilog Testbench Generation Functional Verification Universal Verification Methodology (UVM) Machine Learning Static Analysis ASIC Design Coverage Closure |
| url | https://doi.org/10.5281/zenodo.17587919 |