| _version_ | 1866901613843578880 |
|---|---|
| author | Chun, Dawit |
| author_facet | Chun, Dawit |
| contents | <p><strong>Abstract</strong></p> <p>I present a morphable RISC-V processor capable of dynamically switching between 3-stage (P3), 5-stage (P5), and 7-stage (P7) pipeline configurations to optimize performance across diverse workloads. Shallow pipelines minimize branch misprediction penalties but limit clock frequency, while deep pipelines enable higher frequencies at the cost of increased branch overhead. The design uses bypass multiplexers to reconfigure pipeline depth at runtime, guided by a hybrid AI predictor combining decision trees with perceptron networks. The predictor monitors workload characteristics—branch frequency, CPI overhead, and stall rates—to automatically select the optimal configuration, achieving 90+% prediction accuracy across ten benchmarks. Implemented on a Lattice iCE40 FPGA, the system demonstrates clock frequencies of 4 MHz (P3), 8 MHz (P5), and 12 MHz (P7), with measured performance improvements on both branch-heavy and compute-intensive workloads.</p> |
| format | Recurso digital |
| id | zenodo_https___doi_org_10_5281_zenodo_18006580 |
| institution | Zenodo |
| language | |
| publishDate | 2025 |
| publisher | Zenodo |
| record_format | zenodo |
| spellingShingle | Morphable RISC-V CPU Predictive Tree-Based Perceptron Pipeline Chun, Dawit <p><strong>Abstract</strong></p> <p>I present a morphable RISC-V processor capable of dynamically switching between 3-stage (P3), 5-stage (P5), and 7-stage (P7) pipeline configurations to optimize performance across diverse workloads. Shallow pipelines minimize branch misprediction penalties but limit clock frequency, while deep pipelines enable higher frequencies at the cost of increased branch overhead. The design uses bypass multiplexers to reconfigure pipeline depth at runtime, guided by a hybrid AI predictor combining decision trees with perceptron networks. The predictor monitors workload characteristics—branch frequency, CPI overhead, and stall rates—to automatically select the optimal configuration, achieving 90+% prediction accuracy across ten benchmarks. Implemented on a Lattice iCE40 FPGA, the system demonstrates clock frequencies of 4 MHz (P3), 8 MHz (P5), and 12 MHz (P7), with measured performance improvements on both branch-heavy and compute-intensive workloads.</p> |
| title | Morphable RISC-V CPU Predictive Tree-Based Perceptron Pipeline |
| url | https://doi.org/10.5281/zenodo.18006580 |