Development of Verification Infrastructure to Validate RAM Low Power Features at Unit Level
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| Format: | Recurso digital |
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2022
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| _version_ | 1866901568238911488 |
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| author | Vibha Narayan R Sujatha Hiremath |
| author_facet | Vibha Narayan R Sujatha Hiremath |
| contents | Various low power techniques incorporated in low-power design, particularly in GPU with multiple power islands or voltage islands. The different industrial standard tools and languages that are used in the design process are spoken about, and the design methodology is elaborately explained. RAM power gating at unit level is discussed in detail. A reduction in leakage currents was noticed when standard low power cells are inserted correctly. This is evident from the reduction of leakage current in percentage for sleep mode 98 % of leakage reduction is present and in retention mode depending on the technology node used there is 80 % of leakage reduction. There is also a significant improvement in the CPU time and simulation time and maximum memory utilized. |
| format | Recurso digital |
| id | zenodo_https___doi_org_10_5281_zenodo_18412837 |
| institution | Zenodo |
| language | |
| publishDate | 2022 |
| publisher | Zenodo |
| record_format | zenodo |
| spellingShingle | Development of Verification Infrastructure to Validate RAM Low Power Features at Unit Level Vibha Narayan R Sujatha Hiremath Low power methodology power gating SRAM low power verification. Various low power techniques incorporated in low-power design, particularly in GPU with multiple power islands or voltage islands. The different industrial standard tools and languages that are used in the design process are spoken about, and the design methodology is elaborately explained. RAM power gating at unit level is discussed in detail. A reduction in leakage currents was noticed when standard low power cells are inserted correctly. This is evident from the reduction of leakage current in percentage for sleep mode 98 % of leakage reduction is present and in retention mode depending on the technology node used there is 80 % of leakage reduction. There is also a significant improvement in the CPU time and simulation time and maximum memory utilized. |
| title | Development of Verification Infrastructure to Validate RAM Low Power Features at Unit Level |
| topic | Low power methodology power gating SRAM low power verification. |
| url | https://doi.org/10.5281/zenodo.18412837 |