Verification of Universal Asynchronous Receiver and Transmitter (UART) using System Verilog

Fuente: Zenodo

Saved in:

Bibliographic Details
Main Authors:	M Srinath, Sujatha Hiremath
Format:	Recurso digital
Published:	Zenodo 2022
Subjects:	UART UVM constrained randomization functional and code coverage baud rate generator FIFO SystemVerilog
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Internet