Verification of Universal Asynchronous Receiver and Transmitter (UART) using System Verilog
Fuente:
Zenodo
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Recurso digital |
| Veröffentlicht: |
Zenodo
2022
|
| Schlagworte: | |
| Online-Zugang: | |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| _version_ | 1866901577549217792 |
|---|---|
| author | M Srinath Sujatha Hiremath |
| author_facet | M Srinath Sujatha Hiremath |
| contents | This paper aims at designing a UART using SystemVerilog and verifying the same using a UVM based testbench. UART is one of the most frequently utilized serial communication protocol without the need for a clock excitation. The design includes baud rate generator, control, bus interface, interrupt control and the receiver-transmitter FIFO blocks. Parallel data from system bus are serialized and transmitted and the vice versa process is performed at the receiver end. The verification environment is a reusable and flexible one thereby reducing the complexity and time. Constrained randomization is adopted for random stimulus generation and a functional coverage of 100% and approximately 76.4% code coverage was achieved. |
| format | Recurso digital |
| id | zenodo_https___doi_org_10_5281_zenodo_18413260 |
| institution | Zenodo |
| language | |
| publishDate | 2022 |
| publisher | Zenodo |
| record_format | zenodo |
| spellingShingle | Verification of Universal Asynchronous Receiver and Transmitter (UART) using System Verilog M Srinath Sujatha Hiremath UART UVM constrained randomization functional and code coverage baud rate generator FIFO SystemVerilog This paper aims at designing a UART using SystemVerilog and verifying the same using a UVM based testbench. UART is one of the most frequently utilized serial communication protocol without the need for a clock excitation. The design includes baud rate generator, control, bus interface, interrupt control and the receiver-transmitter FIFO blocks. Parallel data from system bus are serialized and transmitted and the vice versa process is performed at the receiver end. The verification environment is a reusable and flexible one thereby reducing the complexity and time. Constrained randomization is adopted for random stimulus generation and a functional coverage of 100% and approximately 76.4% code coverage was achieved. |
| title | Verification of Universal Asynchronous Receiver and Transmitter (UART) using System Verilog |
| topic | UART UVM constrained randomization functional and code coverage baud rate generator FIFO SystemVerilog |
| url | https://doi.org/10.5281/zenodo.18413260 |