Catechon Hardware Integration Specification: Physical Layer & Fail-Safe Logic
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| Format: | Recurso digital |
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Zenodo
2026
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| _version_ | 1866901186303492096 |
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| author | Kovalevych, Maksym Alekseevich |
| author_facet | Kovalevych, Maksym Alekseevich |
| contents | <p>Technical specification for interfacing FPGA-based active control systems with standard tokamak diagnostics (Mirnov coils) and actuators. Includes fail-safe bypass schematics.</p> |
| format | Recurso digital |
| id | zenodo_https___doi_org_10_5281_zenodo_18472524 |
| institution | Zenodo |
| language | |
| publishDate | 2026 |
| publisher | Zenodo |
| record_format | zenodo |
| spellingShingle | Catechon Hardware Integration Specification: Physical Layer & Fail-Safe Logic Kovalevych, Maksym Alekseevich <p>Technical specification for interfacing FPGA-based active control systems with standard tokamak diagnostics (Mirnov coils) and actuators. Includes fail-safe bypass schematics.</p> |
| title | Catechon Hardware Integration Specification: Physical Layer & Fail-Safe Logic |
| url | https://doi.org/10.5281/zenodo.18472524 |