| _version_ | 1866901542938869760 |
|---|---|
| author | P. Swetha K. Divya Lakshmi Dr. B. Sudarshan |
| author_facet | P. Swetha K. Divya Lakshmi Dr. B. Sudarshan |
| contents | With semiconductor technology's ever-increasing integration capability, today's huge integrated circuits necessitate an ever-increasing quantity of knowledge for testing, resulting in longer test times and higher memory requirements for testers. Larger test data sizes necessitate not only more memory, but also a significant rise in testing time. These continue to be the stumbling block in the system's testing. The foregoing issues are resolved using a technique known as test data compression, which involves lowering the test data volume without compromising the system's overall performance. ISCAS'89 benchmark circuits are known for compressing test sets, hence MINTEST vector creation is used to construct test vectors. The major purpose of the work is to use coding systems like variable length coding and fixed length coding to reduce test data volume and, as a result, test data memory. |
| format | Recurso digital |
| id | zenodo_https___doi_org_10_5281_zenodo_18592053 |
| institution | Zenodo |
| language | |
| publishDate | 2021 |
| publisher | Zenodo |
| record_format | zenodo |
| spellingShingle | An Assessment of Low-Power VLSI Testing Requires A Test Data Compression Architecture P. Swetha K. Divya Lakshmi Dr. B. Sudarshan Compress Tester memory MINTEST vector ISCAS'89. With semiconductor technology's ever-increasing integration capability, today's huge integrated circuits necessitate an ever-increasing quantity of knowledge for testing, resulting in longer test times and higher memory requirements for testers. Larger test data sizes necessitate not only more memory, but also a significant rise in testing time. These continue to be the stumbling block in the system's testing. The foregoing issues are resolved using a technique known as test data compression, which involves lowering the test data volume without compromising the system's overall performance. ISCAS'89 benchmark circuits are known for compressing test sets, hence MINTEST vector creation is used to construct test vectors. The major purpose of the work is to use coding systems like variable length coding and fixed length coding to reduce test data volume and, as a result, test data memory. |
| title | An Assessment of Low-Power VLSI Testing Requires A Test Data Compression Architecture |
| topic | Compress Tester memory MINTEST vector ISCAS'89. |
| url | https://doi.org/10.5281/zenodo.18592053 |