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An Assessment of Low-Power VLSI Testing Requires A Test Data Compression Architecture
An Assessment of Low-Power VLSI Testing Requires A Test Data Compression Architecture
Fuente:
Zenodo
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Bibliographic Details
Main Authors:
P. Swetha
,
K. Divya Lakshmi
,
Dr. B. Sudarshan
Format:
Recurso digital
Published:
Zenodo
2021
Subjects:
Compress
Tester memory
MINTEST vector
ISCAS'89.
Online Access:
Acceder al recurso
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