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| Format: | Recurso digital |
| Language: | English |
| Published: |
Zenodo
2026
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| Subjects: | |
| Online Access: | https://doi.org/10.5281/zenodo.18627662 |
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Table of Contents:
- <h2>Erratum: For instances with N = 63, the execution time was incorrectly reported as 0.6 s. The correct measured value is <em><strong>0.1 s</strong></em>.</h2> <h1>Feedback and independent verification are welcome. Thank you.</h1> <p> </p> <p dir="ltr"><strong>Abstract:</strong></p> <p dir="ltr">This work presents the experimental validation of a generic low-level hardware architecture designed to achieve tractability beyond state-of-the-art barriers for NP-hard optimization. The system solves Longest Path and Hamiltonian Path instances up to the physical limit of 64-bit registers (N=63 nodes) in sub-second time on a consumer mobile processor.</p> <p dir="ltr"><strong>Key Achievements:</strong></p> <ul> <li><strong>The 64-Bit Frontier: Successfully</strong> solved instances of N=63 (Search space \approx 1.9 X 10^{87} permutations) in 0.673 seconds.</li> <li><strong>Constructive Proof:</strong> The complete Hamiltonian path for N=63 is verified and printed, demonstrating 63 unique nodes and zero duplicates.</li> <li><strong>Thermodynamic Invariance:</strong> Stress tests confirm bit-perfect determinism even under extreme thermal throttling (80°C), proving the architecture utilizes physical entropy as a computational resource rather than an error source.</li> </ul> <p dir="ltr"> </p> <p dir="ltr"><strong>Methodology:</strong></p> <p dir="ltr">The architecture operates entirely within CPU registers using bitwise operations (AND, OR, XOR, CTZ) and requires zero external memory allocation. It employs a <strong>Thermodynamic Chaos Engine</strong> to harvest entropy from race conditions and a <strong>Prime-Factor Structural Pruning</strong> heuristic to reduce the search space by ~97.4% in dense topologies.</p> <p dir="ltr"><strong>Conclusion:</strong></p> <p dir="ltr">This work validates that NP-hard industrial optimization is achievable through physics-aware co-design of algorithm and silicon substrate, portable to any modern 64-bit processor (x86, ARM, RISC-V).</p> <p dir="ltr"> </p> <p dir="ltr">lctrnc1@gmail.com</p>