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| Natura: | Recurso digital |
| Lingua: | inglese |
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2026
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| Accesso online: | https://doi.org/10.5281/zenodo.18636347 |
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| _version_ | 1866902203107639296 |
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| author | Pirolo, Andrés Sebastián |
| author_facet | Pirolo, Andrés Sebastián |
| contents | <p><strong>⚠️ Author’s Note (Language and Tooling Disclosure)</strong></p> <p>The author is a native Spanish speaker. A Large Language Model (LLM) was used <strong>exclusively for academic translation, grammar, and formatting</strong>, with the sole purpose of communicating the results clearly and efficiently to the international research community.<br><strong>All algorithmic design, implementation, experimental methodology, and results are entirely human-derived and original.</strong></p> <h2><strong>Abstract / Description</strong></h2> <p>This work presents and validates a <strong>silicon-native computational architecture</strong> for addressing <strong>NP-Hard optimization problems</strong>, with a specific focus on the <strong>Hamiltonian Path Problem on directed (unilateral) graphs</strong>, which constitute one of the <strong>most restrictive and computationally demanding problem classes</strong> due to asymmetric edge constraints and reduced combinatorial symmetry.</p> <p>Unlike conventional approaches that treat the CPU as a high-level software execution platform, the proposed system models the processor as a <strong>physical substrate of logic gates</strong>, leveraging <strong>strictly bitwise operations</strong> and <strong>hardware-level nondeterminism</strong> arising from real silicon behavior.</p> <h2><strong>Key Results</strong></h2> <p>• <strong>Execution Performance</strong><br>Directed Hamiltonian Path instances with <strong>N = 63</strong><br>(search space ≈ 10⁸⁷) were solved in <strong>0.116 seconds</strong> on a standard commercial mobile processor.</p> <p>• <strong>Algorithmic Mechanism</strong><br>The method incorporates <strong>hardware race conditions</strong>, <strong>capacitive noise</strong>, and <strong>L1 cache timing jitter</strong> as controlled entropy sources to facilitate escape from local optima, effectively exploiting <strong>non-ideal physical characteristics of silicon</strong> rather than abstract randomness.</p> <p>• <strong>Problem Class</strong><br>All reported results correspond to <strong>directed (unilateral) graphs</strong>, which are strictly harder than undirected variants due to directionality constraints and reduced path equivalence.</p> <p>• <strong>Implementation and Portability</strong><br>The implementation is written in <strong>pure C / C-style C++</strong>, requires <strong>zero dynamic memory allocation</strong>, and is suitable for deployment on <strong>bare-metal microcontrollers</strong>, <strong>embedded platforms</strong>, and <strong>DSP architectures</strong> with limited memory availability.</p> <h2><strong>Reproducibility and Review</strong></h2> <p>The author welcomes <strong>independent verification, critical review, and replication attempts</strong>.<br>All feedback is appreciated.</p> <p>✉️ <strong>Contact:</strong> <a href="mailto:lctrnc1@gmail.com">lctrnc1@gmail.com</a></p> <p> </p> |
| format | Recurso digital |
| id | zenodo_https___doi_org_10_5281_zenodo_18636347 |
| institution | Zenodo |
| language | eng |
| publishDate | 2026 |
| publisher | Zenodo |
| record_format | zenodo |
| spellingShingle | A Generic Low-Level Solver for NP-Hard Instances (N=63) on Commodity 64-Bit Silicon Breaking the Tractability Barrier: Pirolo, Andrés Sebastián Pvsnp Npvsp Hamiltonian Path Problem Thermodynamic Computing <p><strong>⚠️ Author’s Note (Language and Tooling Disclosure)</strong></p> <p>The author is a native Spanish speaker. A Large Language Model (LLM) was used <strong>exclusively for academic translation, grammar, and formatting</strong>, with the sole purpose of communicating the results clearly and efficiently to the international research community.<br><strong>All algorithmic design, implementation, experimental methodology, and results are entirely human-derived and original.</strong></p> <h2><strong>Abstract / Description</strong></h2> <p>This work presents and validates a <strong>silicon-native computational architecture</strong> for addressing <strong>NP-Hard optimization problems</strong>, with a specific focus on the <strong>Hamiltonian Path Problem on directed (unilateral) graphs</strong>, which constitute one of the <strong>most restrictive and computationally demanding problem classes</strong> due to asymmetric edge constraints and reduced combinatorial symmetry.</p> <p>Unlike conventional approaches that treat the CPU as a high-level software execution platform, the proposed system models the processor as a <strong>physical substrate of logic gates</strong>, leveraging <strong>strictly bitwise operations</strong> and <strong>hardware-level nondeterminism</strong> arising from real silicon behavior.</p> <h2><strong>Key Results</strong></h2> <p>• <strong>Execution Performance</strong><br>Directed Hamiltonian Path instances with <strong>N = 63</strong><br>(search space ≈ 10⁸⁷) were solved in <strong>0.116 seconds</strong> on a standard commercial mobile processor.</p> <p>• <strong>Algorithmic Mechanism</strong><br>The method incorporates <strong>hardware race conditions</strong>, <strong>capacitive noise</strong>, and <strong>L1 cache timing jitter</strong> as controlled entropy sources to facilitate escape from local optima, effectively exploiting <strong>non-ideal physical characteristics of silicon</strong> rather than abstract randomness.</p> <p>• <strong>Problem Class</strong><br>All reported results correspond to <strong>directed (unilateral) graphs</strong>, which are strictly harder than undirected variants due to directionality constraints and reduced path equivalence.</p> <p>• <strong>Implementation and Portability</strong><br>The implementation is written in <strong>pure C / C-style C++</strong>, requires <strong>zero dynamic memory allocation</strong>, and is suitable for deployment on <strong>bare-metal microcontrollers</strong>, <strong>embedded platforms</strong>, and <strong>DSP architectures</strong> with limited memory availability.</p> <h2><strong>Reproducibility and Review</strong></h2> <p>The author welcomes <strong>independent verification, critical review, and replication attempts</strong>.<br>All feedback is appreciated.</p> <p>✉️ <strong>Contact:</strong> <a href="mailto:lctrnc1@gmail.com">lctrnc1@gmail.com</a></p> <p> </p> |
| title | A Generic Low-Level Solver for NP-Hard Instances (N=63) on Commodity 64-Bit Silicon Breaking the Tractability Barrier: |
| topic | Pvsnp Npvsp Hamiltonian Path Problem Thermodynamic Computing |
| url | https://doi.org/10.5281/zenodo.18636347 |