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Design of Novel 64- bit Multiplier-Accumulator using Vedic Multiplier & Hybrid Adder
Design of Novel 64- bit Multiplier-Accumulator using Vedic Multiplier & Hybrid Adder
Fuente:
Zenodo
Saved in:
Bibliographic Details
Main Authors:
A Akash
,
Mahanthesh K
,
Manjesh M
,
Y T Lokesh
,
Prof. K Sujatha
Format:
Recurso digital
Language:
English
Published:
Zenodo
2026
Subjects:
Vedic multiplier, Urdhva Tiryagbhyam, hybrid adder, MAC unit, energy efficiency.
Online Access:
Acceder al recurso
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Internet
https://doi.org/10.5281/zenodo.18708823
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