Design of Novel 64- bit Multiplier-Accumulator using Vedic Multiplier & Hybrid Adder
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2026
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| _version_ | 1866901963627560960 |
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| author | A Akash Mahanthesh K Manjesh M Y T Lokesh Prof. K Sujatha |
| author_facet | A Akash Mahanthesh K Manjesh M Y T Lokesh Prof. K Sujatha |
| contents | <p><em><span lang="EN-US">Multiplication and accumulation form the core of numerous digital applications, including<span> </span>image<span> </span>processing,<span> </span>AI<span> </span>inference,<span> </span>and<span> </span>embedded<span> </span>system<span> </span>operations.<span> </span>This<span> </span>paper<span> </span>presents a<span> </span>64-bit<span> </span>multiplier-accumulator<span> </span>(MAC)<span> </span>architecture<span> </span>that<span> </span>incorporates<span> </span>the Urdhva<span> </span>Tiryagbhyam method from Vedic mathematics for fast and efficient multiplication. The proposed design leverages a hybrid adder architecture, combining Carry Skip Adder (CSKA) and Ripple Carry Adder<span> </span>(RCA),<span> </span>to<span> </span>achieve<span> </span>a<span> </span>balance<span> </span>between<span> </span>speed,<span> </span>power<span> </span>efficiency,<span> </span>and<span> </span>chip<span> </span>area.<span> </span>Implemented in Verilog HDL and synthesized using Xilinx Vivado, the proposed unit exhibits significant enhancements in delay, area, and power consumption when compared with conventional <span>approaches.</span></span></em></p> |
| format | Recurso digital |
| id | zenodo_https___doi_org_10_5281_zenodo_18708823 |
| institution | Zenodo |
| language | eng |
| publishDate | 2026 |
| publisher | Zenodo |
| record_format | zenodo |
| spellingShingle | Design of Novel 64- bit Multiplier-Accumulator using Vedic Multiplier & Hybrid Adder A Akash Mahanthesh K Manjesh M Y T Lokesh Prof. K Sujatha Vedic multiplier, Urdhva Tiryagbhyam, hybrid adder, MAC unit, energy efficiency. <p><em><span lang="EN-US">Multiplication and accumulation form the core of numerous digital applications, including<span> </span>image<span> </span>processing,<span> </span>AI<span> </span>inference,<span> </span>and<span> </span>embedded<span> </span>system<span> </span>operations.<span> </span>This<span> </span>paper<span> </span>presents a<span> </span>64-bit<span> </span>multiplier-accumulator<span> </span>(MAC)<span> </span>architecture<span> </span>that<span> </span>incorporates<span> </span>the Urdhva<span> </span>Tiryagbhyam method from Vedic mathematics for fast and efficient multiplication. The proposed design leverages a hybrid adder architecture, combining Carry Skip Adder (CSKA) and Ripple Carry Adder<span> </span>(RCA),<span> </span>to<span> </span>achieve<span> </span>a<span> </span>balance<span> </span>between<span> </span>speed,<span> </span>power<span> </span>efficiency,<span> </span>and<span> </span>chip<span> </span>area.<span> </span>Implemented in Verilog HDL and synthesized using Xilinx Vivado, the proposed unit exhibits significant enhancements in delay, area, and power consumption when compared with conventional <span>approaches.</span></span></em></p> |
| title | Design of Novel 64- bit Multiplier-Accumulator using Vedic Multiplier & Hybrid Adder |
| topic | Vedic multiplier, Urdhva Tiryagbhyam, hybrid adder, MAC unit, energy efficiency. |
| url | https://doi.org/10.5281/zenodo.18708823 |