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| Format: | Recurso digital |
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Zenodo
2026
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| Online Access: | https://doi.org/10.5281/zenodo.18913865 |
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Table of Contents:
- <p>This submission presents the Gelron Architecture, a theoretical design study and preliminary engineering specification for a volumetric, solid-state optical Application-Specific Integrated Circuit (ASIC). Designed specifically for Ternary Large Language Model (LLM) inference under the BitNet b1.58 paradigm, the Gelron ASIC functions as a heterogeneous optical-electronic co-processor. It executes <span>$O(N^2)$</span> ternary matrix multiplications optically through a passive 3D-printed polymer mesh, while leveraging a bonded Silicon CMOS interposer for <span>$O(N)$</span> operations, KV-caching, and signal phase-resets. The specification resolves historic optomechanical limitations of 3D optical computing by introducing suspended isotropic waveguides for polarization integrity, in-situ holographic calibration, volumetric EDFA gain-loss reconciliation, and a Wavelength-Division Multiplexed (WDM) throughput model. The resulting architecture offers a physically manufacturable pathway to ultra-low-energy, sub-microsecond AI acceleration.</p>