NEURA: A Unified and Retargetable Compilation Framework for Coarse-Grained Reconfigurable Architectures
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| Natura: | Recurso digital |
| Lingua: | inglese |
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2026
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| author | Li, Shangkun Ge, Jinming Tao, Diyuan Li, Zeyu Liang, Jiawei Du, Linfeng Xu, Jiang Zhang, Wei Tan, Cheng |
| author_facet | Li, Shangkun Ge, Jinming Tao, Diyuan Li, Zeyu Liang, Jiawei Du, Linfeng Xu, Jiang Zhang, Wei Tan, Cheng |
| contents | <p>Coarse-Grained Reconfigurable Architectures (CGRAs) are a promising and versatile accelerator platform, offering a balance between the performance and efficiency of specialized accelerators and the software programmability. However, their full potential is severely hindered by control flow in accelerated kernels, as the control flow (e.g., loops, branches) is fundamentally incompatible with the parallel, data-driven CGRA fabric. Prior strategies to resolve this mismatch in CGRA kernel acceleration are either inefficient, sacrificing performance for generality, or lack generality by remaining tightly coupled to specific hardware primitives. Thus, a general and unified solution for efficient CGRA kernel acceleration remains elusive.</p> <p>This paper introduces NEURA, a unified and retargetable compilation framework that systematically resolves the control-dataflow mismatch in CGRAs. NEURA's core innovation is a novel, pure dataflow intermediate representation (IR) built on a predicated type system. In this IR, control contexts are embedded as a predicate within each data, making control an intrinsic property of data. This mechanism enables NEURA to systematically flatten complex control flow into a single unified dataflow graph. This unified representation decouples kernel representation from hardware, empowering NEURA to retarget diverse CGRAs with different execution models and microarchitectural features. Our evaluation shows NEURA achieves state-of-the-art (SOTA) performance when targeted to a high-performance spatio-temporal CGRA, delivering a 2.40x speedup over the leading high-performance baseline. It also provides a competitive solution against the SOTA low-power CGRA when retargeted to a spatial-only CGRA.</p> |
| format | Recurso digital |
| id | zenodo_https___doi_org_10_5281_zenodo_18982337 |
| institution | Zenodo |
| language | eng |
| publishDate | 2026 |
| publisher | Zenodo |
| record_format | zenodo |
| spellingShingle | NEURA: A Unified and Retargetable Compilation Framework for Coarse-Grained Reconfigurable Architectures Li, Shangkun Ge, Jinming Tao, Diyuan Li, Zeyu Liang, Jiawei Du, Linfeng Xu, Jiang Zhang, Wei Tan, Cheng Dataflow Compiler CGRA Reconfigurable Architecture Dataflow Architecture <p>Coarse-Grained Reconfigurable Architectures (CGRAs) are a promising and versatile accelerator platform, offering a balance between the performance and efficiency of specialized accelerators and the software programmability. However, their full potential is severely hindered by control flow in accelerated kernels, as the control flow (e.g., loops, branches) is fundamentally incompatible with the parallel, data-driven CGRA fabric. Prior strategies to resolve this mismatch in CGRA kernel acceleration are either inefficient, sacrificing performance for generality, or lack generality by remaining tightly coupled to specific hardware primitives. Thus, a general and unified solution for efficient CGRA kernel acceleration remains elusive.</p> <p>This paper introduces NEURA, a unified and retargetable compilation framework that systematically resolves the control-dataflow mismatch in CGRAs. NEURA's core innovation is a novel, pure dataflow intermediate representation (IR) built on a predicated type system. In this IR, control contexts are embedded as a predicate within each data, making control an intrinsic property of data. This mechanism enables NEURA to systematically flatten complex control flow into a single unified dataflow graph. This unified representation decouples kernel representation from hardware, empowering NEURA to retarget diverse CGRAs with different execution models and microarchitectural features. Our evaluation shows NEURA achieves state-of-the-art (SOTA) performance when targeted to a high-performance spatio-temporal CGRA, delivering a 2.40x speedup over the leading high-performance baseline. It also provides a competitive solution against the SOTA low-power CGRA when retargeted to a spatial-only CGRA.</p> |
| title | NEURA: A Unified and Retargetable Compilation Framework for Coarse-Grained Reconfigurable Architectures |
| topic | Dataflow Compiler CGRA Reconfigurable Architecture Dataflow Architecture |
| url | https://doi.org/10.5281/zenodo.18982337 |