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| Main Authors: | , , , , , |
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| Format: | Recurso digital |
| Language: | |
| Published: |
Zenodo
2026
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| Online Access: | https://doi.org/10.5281/zenodo.19054459 |
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Table of Contents:
- <p><em><span>This paper represents an in-depth investigation into the design and evaluation of an ultra-low-leakage, wide-range voltage level shifter tailored for modern System-on-Chip (SoC) architectures. In these systems, diverse modules function across multiple voltage domains to optimize performance and energy consumption, necessitating reliable signal bridging via voltage level shifters (LS). Conventional LS topologies, however, face challenges like elevated leakage currents, diminished output amplitude, and prolonged propagation delays, especially in sub-threshold modes. The proposed LS, realized in 45nm CMOS technology, integrates leakage-suppressing transistors to curtail static dissipation, hysteresis mechanisms to rectify amplitude issues, and low-threshold NMOS elements to boost switching velocity. Simulation data from 45nm CMOS indicate a broad conversion spectrum spanning sub-threshold 0.2V to 1.2V, with notable enhancements in delay minimization and energy conservation relative to traditional designs. This innovative architecture is particularly advantageous for energy-frugal IoT platforms, mobile electronics, and power-optimized VLSI frameworks.</span></em></p>