| _version_ | 1866901107933970432 |
|---|---|
| author | International Journal of Technology, Leadership and Sciences |
| author_facet | International Journal of Technology, Leadership and Sciences |
| contents | <p><span>Reconfigurable computer architectures for digital signal processing (DSP) applications that require high performance and low energy consumption are examined in this research. It draws attention to the rising need for flexible hardware platforms that can handle the computational demands of contemporary DSP workloads while using the least amount of power. The study looks at how coarse-grained reconfigurable architectures (CGRAs) and field-programmable gate arrays (FPGAs) can speed up signal processing activities like image processing, FFT, and filtering. Through the use of pipelining, parallelism, and dynamic reconfiguration, the suggested architectures significantly reduce latency and increase throughput. The trade-offs between adaptability, performance, and energy efficiency in architecture are also examined in the article. There is discussion of optimization strategies including runtime reconfiguration, hardware-software co-design, and resource sharing.</span></p> <p> </p> |
| format | Recurso digital |
| id | zenodo_https___doi_org_10_5281_zenodo_19128320 |
| institution | Zenodo |
| language | |
| publishDate | 2026 |
| publisher | Zenodo |
| record_format | zenodo |
| spellingShingle | RECONFIGURABLE COMPUTING ARCHITECTURES FOR HIGH-PERFORMANCE AND ENERGY-EFFICIENT DSP APPLICATIONS International Journal of Technology, Leadership and Sciences Reconfigurable Computing Digital Signal Processing (DSP) Field-Programmable Gate Arrays (FPGAs) Energy Efficiency <p><span>Reconfigurable computer architectures for digital signal processing (DSP) applications that require high performance and low energy consumption are examined in this research. It draws attention to the rising need for flexible hardware platforms that can handle the computational demands of contemporary DSP workloads while using the least amount of power. The study looks at how coarse-grained reconfigurable architectures (CGRAs) and field-programmable gate arrays (FPGAs) can speed up signal processing activities like image processing, FFT, and filtering. Through the use of pipelining, parallelism, and dynamic reconfiguration, the suggested architectures significantly reduce latency and increase throughput. The trade-offs between adaptability, performance, and energy efficiency in architecture are also examined in the article. There is discussion of optimization strategies including runtime reconfiguration, hardware-software co-design, and resource sharing.</span></p> <p> </p> |
| title | RECONFIGURABLE COMPUTING ARCHITECTURES FOR HIGH-PERFORMANCE AND ENERGY-EFFICIENT DSP APPLICATIONS |
| topic | Reconfigurable Computing Digital Signal Processing (DSP) Field-Programmable Gate Arrays (FPGAs) Energy Efficiency |
| url | https://doi.org/10.5281/zenodo.19128320 |