FPGA Implementation of Single Precision Floating Point Multiplier using Booth Recoding Algorithm
Fuente:
Zenodo
Guardado en:
| Autor principal: | |
|---|---|
| Formato: | Recurso digital |
| Publicado: |
Zenodo
2026
|
| Materias: | |
| Acceso en línea: | |
| Etiquetas: |
Agregar Etiqueta
Sin Etiquetas, Sea el primero en etiquetar este registro!
|
| _version_ | 1866901631787859968 |
|---|---|
| author | Prince Mishra |
| author_facet | Prince Mishra |
| contents | Through this paper, we focus on implementing a Single Precision Floating Multiplier using IEEE 754 Standards. By reducing partial product generation and addition units, this implementation offers benefits such as faster results, reduced power consumption and reduction in the utilization of hardware resources. Moreover, the implementation deals with multiplication of both signed and unsigned numbers. The paper presents a comparative analysis with a 32-bit multiplier performance in terms of power consumption and FPGA hardware resource utilization. The proposed 32-bit multiplier is designed using Verilog HDL and implemented through Xilinx Vivado 2025.1 software for Xilinx Virtex-7 FPGA. |
| format | Recurso digital |
| id | zenodo_https___doi_org_10_5281_zenodo_19185375 |
| institution | Zenodo |
| language | |
| publishDate | 2026 |
| publisher | Zenodo |
| record_format | zenodo |
| spellingShingle | FPGA Implementation of Single Precision Floating Point Multiplier using Booth Recoding Algorithm Prince Mishra FPGA; Booth Recording; Single Precision; signed multiplier; Verilog HDL. Through this paper, we focus on implementing a Single Precision Floating Multiplier using IEEE 754 Standards. By reducing partial product generation and addition units, this implementation offers benefits such as faster results, reduced power consumption and reduction in the utilization of hardware resources. Moreover, the implementation deals with multiplication of both signed and unsigned numbers. The paper presents a comparative analysis with a 32-bit multiplier performance in terms of power consumption and FPGA hardware resource utilization. The proposed 32-bit multiplier is designed using Verilog HDL and implemented through Xilinx Vivado 2025.1 software for Xilinx Virtex-7 FPGA. |
| title | FPGA Implementation of Single Precision Floating Point Multiplier using Booth Recoding Algorithm |
| topic | FPGA; Booth Recording; Single Precision; signed multiplier; Verilog HDL. |
| url | https://doi.org/10.5281/zenodo.19185375 |