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2025
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| Accesso online: | https://doi.org/10.5281/zenodo.19205956 |
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| _version_ | 1866902031349841920 |
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| author | Wzorek, Piotr |
| author_facet | Wzorek, Piotr |
| contents | <p>This repository is intended to reproduce and run experiments for a FPGA implementation of event-based audio data processing system for spoken word classification.<br>The system employs an <strong>event-by-event processing</strong> approach using graph neural networks. The weights provided in the project enable processing of spoken digits and were obtained through training on the Spiking Heidelberg Digits Dataset (SHD).</p> <p>The repository includes all necessary hardware modules (SystemVerilog RTL files), along with the required IP cores and memory initialization files.</p> <p>The data and implementation are associated with the following publication:</p> <p><strong>Hardware-accelerated event-graph neural networks for low-latency time-series classification on SoC FPGA</strong><br>Hiroshi Nakano, Krzysztof Błachut, Kamil Jeziorek, Piotr Wzorek, Manon Dampfhoffer, Thomas Mesquida, Hiroaki Nishi, Tomasz Kryjak, Thomas Dalgaty.</p> <p>In: Applied Reconfigurable Computing: Architectures, Tools, and Applications – ARC 2025 Proceedings,<br>21st International Symposium, ARC 2025 – Applied Reconfigurable Computing,<br>Seville, Spain, April 9–11, 2025.<br>Published by Springer in the Lecture Notes in Computer Science (LNCS 15594), pp. 51–68.<br>ISBN: 978-3-031-87994-4, eISBN: 978-3-031-87995-1.</p> <p> </p> <p>This work was supported by the Polish National Science Centre project 2024/53/N/ST6/04331.</p> |
| format | Recurso digital |
| id | zenodo_https___doi_org_10_5281_zenodo_19205956 |
| institution | Zenodo |
| language | |
| publishDate | 2025 |
| publisher | Zenodo |
| record_format | zenodo |
| spellingShingle | Hardware-accelerated event-graph neural networks for low-latency time-series classification on SoC FPGA Wzorek, Piotr <p>This repository is intended to reproduce and run experiments for a FPGA implementation of event-based audio data processing system for spoken word classification.<br>The system employs an <strong>event-by-event processing</strong> approach using graph neural networks. The weights provided in the project enable processing of spoken digits and were obtained through training on the Spiking Heidelberg Digits Dataset (SHD).</p> <p>The repository includes all necessary hardware modules (SystemVerilog RTL files), along with the required IP cores and memory initialization files.</p> <p>The data and implementation are associated with the following publication:</p> <p><strong>Hardware-accelerated event-graph neural networks for low-latency time-series classification on SoC FPGA</strong><br>Hiroshi Nakano, Krzysztof Błachut, Kamil Jeziorek, Piotr Wzorek, Manon Dampfhoffer, Thomas Mesquida, Hiroaki Nishi, Tomasz Kryjak, Thomas Dalgaty.</p> <p>In: Applied Reconfigurable Computing: Architectures, Tools, and Applications – ARC 2025 Proceedings,<br>21st International Symposium, ARC 2025 – Applied Reconfigurable Computing,<br>Seville, Spain, April 9–11, 2025.<br>Published by Springer in the Lecture Notes in Computer Science (LNCS 15594), pp. 51–68.<br>ISBN: 978-3-031-87994-4, eISBN: 978-3-031-87995-1.</p> <p> </p> <p>This work was supported by the Polish National Science Centre project 2024/53/N/ST6/04331.</p> |
| title | Hardware-accelerated event-graph neural networks for low-latency time-series classification on SoC FPGA |
| url | https://doi.org/10.5281/zenodo.19205956 |