Optimizing Digital Signal Processing with Half-Precision Floating-Point Arithmetic

Fuente: Zenodo

Saved in:

Bibliographic Details
Main Author:	Dr. Elianore Quasar and Dr. Kaia Rykhard
Format:	Recurso digital
Published:	Zenodo 2019
Subjects:	Half precision IEEE754 floating point Multiplier adder subtractor QuartusII Verilog hardware descriptive language (HDL).
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Internet