| _version_ | 1866901084018049024 |
|---|---|
| author | Dr. Elianore Quasar and Dr. Kaia Rykhard |
| author_facet | Dr. Elianore Quasar and Dr. Kaia Rykhard |
| contents | <p>—For dealing with digital signals in real time, parameters like, speed of operation, hardware requirement, power and area, must take into consideration Implementation of FFT, with less number of logic gates which helps to reduce area and power required for the design. With this motto multipliers are replaced with pass logic. To represent twiddle factors, standard IEEE floating point format is used. By considering The end user application, twiddle factors are represented in half precision format. So that it helps to increase the speed of application. FFT is completed with complex floating point multiplier, complex floating point adder/subtractor. All design is implemented in Verilog HDL in Quartus II web edition for Cyclone 4E FPGA family. The Synthesized RTL description is tested /simulated in ModelSim simulator</p> |
| format | Recurso digital |
| id | zenodo_https___doi_org_10_5281_zenodo_19304546 |
| institution | Zenodo |
| language | |
| publishDate | 2019 |
| publisher | Zenodo |
| record_format | zenodo |
| spellingShingle | Optimizing Digital Signal Processing with Half-Precision Floating-Point Arithmetic Dr. Elianore Quasar and Dr. Kaia Rykhard Half precision IEEE754 floating point Multiplier adder subtractor QuartusII Verilog hardware descriptive language (HDL). <p>—For dealing with digital signals in real time, parameters like, speed of operation, hardware requirement, power and area, must take into consideration Implementation of FFT, with less number of logic gates which helps to reduce area and power required for the design. With this motto multipliers are replaced with pass logic. To represent twiddle factors, standard IEEE floating point format is used. By considering The end user application, twiddle factors are represented in half precision format. So that it helps to increase the speed of application. FFT is completed with complex floating point multiplier, complex floating point adder/subtractor. All design is implemented in Verilog HDL in Quartus II web edition for Cyclone 4E FPGA family. The Synthesized RTL description is tested /simulated in ModelSim simulator</p> |
| title | Optimizing Digital Signal Processing with Half-Precision Floating-Point Arithmetic |
| topic | Half precision IEEE754 floating point Multiplier adder subtractor QuartusII Verilog hardware descriptive language (HDL). |
| url | https://doi.org/10.5281/zenodo.19304546 |