HEXA-WAFER: Wafer-Scale Engine with 20736 Streaming Multiprocessors from n=6
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| Format: | Recurso digital |
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2026
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| _version_ | 1866901114307215360 |
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| author | Park, Min Woo |
| author_facet | Park, Min Woo |
| contents | We present HEXA-WAFER, a wafer-scale computing engine that tiles \sigma^2 = 144 HEXA-1 compute tiles on a 300 mm silicon wafer, achieving \sigma^4 = 20{,}736 streaming multiprocessors (SMs), \sigma^3 \cdot J_2 = 41{,}472 GB (\sim41.5 TB) of integrated memory, and \sim72 PFLOPS peak FP8 throughput---all derived from the arithmetic functions of the perfect number n = 6. Each tile replicates the HEXA-1 SoC specification (\sigma^2 = 144 SMs, \sigma \cdot J_2 = 288 GB memory), and tiles communicate via an on-wafer mesh interconnect with \tau = 4 nearest-neighbor links per tile at \sim1 TB/s each. A hierarchical optical overlay provides long-range communication across the wafer. The total power envelope of \sim35 kW is managed through \sigma - \tau = 8 power delivery zones, \tau = 4 cooling mani |
| format | Recurso digital |
| id | zenodo_https___doi_org_10_5281_zenodo_19361500 |
| institution | Zenodo |
| language | |
| publishDate | 2026 |
| publisher | Zenodo |
| record_format | zenodo |
| spellingShingle | HEXA-WAFER: Wafer-Scale Engine with 20736 Streaming Multiprocessors from n=6 Park, Min Woo wafer-scale chip-architecture n=6 perfect-number large-scale-computing We present HEXA-WAFER, a wafer-scale computing engine that tiles \sigma^2 = 144 HEXA-1 compute tiles on a 300 mm silicon wafer, achieving \sigma^4 = 20{,}736 streaming multiprocessors (SMs), \sigma^3 \cdot J_2 = 41{,}472 GB (\sim41.5 TB) of integrated memory, and \sim72 PFLOPS peak FP8 throughput---all derived from the arithmetic functions of the perfect number n = 6. Each tile replicates the HEXA-1 SoC specification (\sigma^2 = 144 SMs, \sigma \cdot J_2 = 288 GB memory), and tiles communicate via an on-wafer mesh interconnect with \tau = 4 nearest-neighbor links per tile at \sim1 TB/s each. A hierarchical optical overlay provides long-range communication across the wafer. The total power envelope of \sim35 kW is managed through \sigma - \tau = 8 power delivery zones, \tau = 4 cooling mani |
| title | HEXA-WAFER: Wafer-Scale Engine with 20736 Streaming Multiprocessors from n=6 |
| topic | wafer-scale chip-architecture n=6 perfect-number large-scale-computing |
| url | https://doi.org/10.5281/zenodo.19361500 |