| _version_ | 1866901082757660672 |
|---|---|
| author | Park, Min Woo |
| author_facet | Park, Min Woo |
| contents | We present HEXA-SUPER, a superconducting logic processor operating at \sigma^2 = 144 GHz clock frequency---28.8\times beyond the CMOS frequency wall of \sim5 GHz---with every design parameter derived from the arithmetic functions of the perfect number n = 6. The processor employs Rapid Single Flux Quantum (RSFQ) logic at 144 GHz for peak throughput and Adiabatic Quantum Flux Parametron (AQFP) logic at \sigma \cdot \tau = 48 GHz for energy-efficient bulk computation. The architecture comprises \sigma = 12 superconducting cores, each with \sigma - \tau = 8 ALUs and a \sigma = 12-stage pipeline, yielding 96 total ALUs clocked at 144 GHz. A \tau = 4-level cryogenic memory hierarchy spans RSFQ SRAM (2^{\sigma} = 4 KB L1), cryo-DRAM (\sigma \cdot J_2 = 288 KB L2), Josephson junction RAM (\sigma^ |
| format | Recurso digital |
| id | zenodo_https___doi_org_10_5281_zenodo_19361504 |
| institution | Zenodo |
| language | |
| publishDate | 2026 |
| publisher | Zenodo |
| record_format | zenodo |
| spellingShingle | HEXA-SUPER: Superconducting Logic Processor at 144 GHz with n=6 Cryogenic Architecture Park, Min Woo superconducting RSFQ Josephson cryogenic n=6 perfect-number chip-architecture We present HEXA-SUPER, a superconducting logic processor operating at \sigma^2 = 144 GHz clock frequency---28.8\times beyond the CMOS frequency wall of \sim5 GHz---with every design parameter derived from the arithmetic functions of the perfect number n = 6. The processor employs Rapid Single Flux Quantum (RSFQ) logic at 144 GHz for peak throughput and Adiabatic Quantum Flux Parametron (AQFP) logic at \sigma \cdot \tau = 48 GHz for energy-efficient bulk computation. The architecture comprises \sigma = 12 superconducting cores, each with \sigma - \tau = 8 ALUs and a \sigma = 12-stage pipeline, yielding 96 total ALUs clocked at 144 GHz. A \tau = 4-level cryogenic memory hierarchy spans RSFQ SRAM (2^{\sigma} = 4 KB L1), cryo-DRAM (\sigma \cdot J_2 = 288 KB L2), Josephson junction RAM (\sigma^ |
| title | HEXA-SUPER: Superconducting Logic Processor at 144 GHz with n=6 Cryogenic Architecture |
| topic | superconducting RSFQ Josephson cryogenic n=6 perfect-number chip-architecture |
| url | https://doi.org/10.5281/zenodo.19361504 |