:: Library Catalog

Image de couverture de livre

Enregistré dans:

Détails bibliographiques
Auteurs principaux:	Selg, Hardi, Shibin, Konstantin, Tsertov, Anton, Jenihhin, Maksim, Ellervee, Peeter, Raik, Jaan
Format:	Recurso digital
Langue:
Publié:	Zenodo 2024
Accès en ligne:	https://doi.org/10.5281/zenodo.19443946
Tags:	Ajouter un tag Pas de tags, Soyez le premier à ajouter un tag!

Documents similaires

DeepVigor+: Scalable and Accurate Semi-Analytical Fault Resilience Analysis for Deep Neural Network
par: Ahmadilivani, Mohammad Hasan, et autres
Publié: (2024)

Cost-Effective Fault Tolerance for CNNs Using Parameter Vulnerability Based Hardening and Pruning
par: Ahmadilivani, Mohammad Hasan, et autres
Publié: (2024)

Exploration of Activation Fault Reliability in Quantized Systolic Array-Based DNN Accelerators
par: Taheri, Mahdi, et autres
Publié: (2024)

ProAct: Progressive Training for Hybrid Clipped Activation Function to Enhance Resilience of DNNs
par: Mousavi, Seyedhamidreza, et autres
Publié: (2024)

AdAM: Adaptive Approximate Multiplier for Fault Tolerance in DNN Accelerators
par: Taheri, Mahdi, et autres
Publié: (2024)

Implementing and Optimizing an Open-Source SD-card Host Controller for RISC-V SoCs
par: Vanoni, Axel, et autres
Publié: (2026)

AdAM: Adaptive Fault-Tolerant Approximate Multiplier for Edge DNN Accelerators
par: Taheri, Mahdi, et autres
Publié: (2024)

Fused-Tiled Layers: Minimizing Data Movement on RISC-V SoCs with Software-Managed Caches
par: Jung, Victor J. B., et autres
Publié: (2025)

Architectural Solutions for High-Speed Data Processing Demands of CERN LHC Detectors with FPGA and High-Level Synthesis
par: Devadze, Sergei, et autres
Publié: (2024)

DRsam: Detection of Fault-Based Microarchitectural Side-Channel Attacks in RISC-V Using Statistical Preprocessing and Association Rule Mining
par: Hassan, Muhammad, et autres
Publié: (2025)

Evaluating IOMMU-Based Shared Virtual Addressing for RISC-V Embedded Heterogeneous SoCs
par: Koenig, Cyril, et autres
Publié: (2025)

FORTALESA: Fault-Tolerant Reconfigurable Systolic Array for DNN Inference
par: Cherezova, Natalia, et autres
Publié: (2025)

Flexible Vector Integration in Embedded RISC-V SoCs for End to End CNN Inference Acceleration
par: Lyalikov, Dmitri
Publié: (2025)

System-Level Isolation for Mixed-Criticality RISC-V SoCs: A "World" Reality Check
par: Cunha, Luis, et autres
Publié: (2026)

SAFFIRA: a Framework for Assessing the Reliability of Systolic-Array-Based DNN Accelerators
par: Taheri, Mahdi, et autres
Publié: (2024)

Trikarenos: Design and Experimental Characterization of a Fault-Tolerant 28nm RISC-V-based SoC
par: Rogenmoser, Michael, et autres
Publié: (2024)

Chiplet-Based RISC-V SoC with Modular AI Acceleration
par: Bharadwaj, Suhas Suresh, et autres
Publié: (2025)

SoCks - Simplifying Firmware and Software Integration for Heterogeneous SoCs
par: Fuchs, Marvin, et autres
Publié: (2025)

TOP: Towards Open & Predictable Heterogeneous SoCs
par: Valente, Luca, et autres
Publié: (2024)

FeNN-DMA: A RISC-V SoC for SNN acceleration
par: Aizaz, Zainab, et autres
Publié: (2025)

Multi-DNN Inference of Sparse Models on Edge SoCs
par: Luo, Jiawei, et autres
Publié: (2026)

IMS: Intelligent Hardware Monitoring System for Secure SoCs
par: Foudhaili, Wadid, et autres
Publié: (2026)

A Heterogeneous RISC-V based SoC for Secure Nano-UAV Navigation
par: Valente, Luca, et autres
Publié: (2024)

Bare-Metal RISC-V + NVDLA SoC for Efficient Deep Learning Inference
par: Kumar, Vineet, et autres
Publié: (2025)

A Scalable Resource Management Layer for FPGA SoCs in 6G Radio Units
par: Bartzoudis, Nikolaos, et autres
Publié: (2025)

Characterizing and Optimizing Real-Time Optimal Control for Embedded SoCs
par: Dong, Kris Shengjun, et autres
Publié: (2024)

Open-Source Heterogeneous SoCs for AI: The PULP Platform Experience
par: Conti, Francesco, et autres
Publié: (2024)

Optimizing DNN Inference on Multi-Accelerator SoCs at Training-time
par: Risso, Matteo, et autres
Publié: (2024)

Design and Implementation of a RISC-V SoC with Custom DSP Accelerators for Edge Computing
par: Yadav, Priyanshu
Publié: (2025)

An Efficient Architecture for Edge AI Federated Learning With Homomorphic Encryption
par: Rahbari, Dadmehr, et autres
Publié: (2025)

Automated Formal Verification of Area-Optimized Safety Registers in Automotive SoCs
par: Zhang, Shuhang, et autres
Publié: (2025)

NeCTAr: A Heterogeneous RISC-V SoC for Language Model Inference in Intel 16
par: Schmulbach, Viansa, et autres
Publié: (2025)

HULK-V: a Heterogeneous Ultra-low-power Linux capable RISC-V SoC
par: Valente, Luca, et autres
Publié: (2022)

RISC-V Functional Safety for Autonomous Automotive Systems: An Analytical Framework and Research Roadmap for ML-Assisted Certification
par: Andreasyan, Nick, et autres
Publié: (2026)

Hybrid Cryptographic Monitoring System for Side-Channel Attack Detection on PYNQ SoCs
par: Chinnasami, Nishant, et autres
Publié: (2025)

PARSAC: Fast, Human-quality Floorplanning for Modern SoCs with Complex Design Constraints
par: Mostafa, Hesham, et autres
Publié: (2024)

Siracusa: A 16 nm Heterogenous RISC-V SoC for Extended Reality with At-MRAM Neural Engine
par: Prasad, Arpan Suravi, et autres
Publié: (2023)

Basilisk: An End-to-End Open-Source Linux-Capable RISC-V SoC in 130nm CMOS
par: Scheffler, Paul, et autres
Publié: (2024)

Combining Fault Tolerance Techniques and COTS SoC Accelerators for Payload Processing in Space
par: Leon, Vasileios, et autres
Publié: (2025)

SoK: Trusted Execution in SoC-FPGAs
par: Perkins, Garrett, et autres
Publié: (2025)