RST: Random-Access Hardware Sequence Compression — Artifact
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Zenodo
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| Autori principali: | , , , |
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| Natura: | Recurso digital |
| Lingua: | inglese |
| Pubblicazione: |
Zenodo
2026
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| _version_ | 1866902257656659968 |
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| author | Chu, Nolan Lee, Yoon Panwar, Gagandeep Jian, Xun |
| author_facet | Chu, Nolan Lee, Yoon Panwar, Gagandeep Jian, Xun |
| contents | <p>Artifact for "Random-Access Hardware Sequence Compression" (ISCA 2026).</p> <p>This artifact contains:<br>- Software RST compression implementation (C++) for reproducing compression ratio results (Fig. 18, Fig. 19)<br>- SystemVerilog RTL for the RST compressor and decompressor, compilable with Verilator for functional verification and performance metric extraction<br>- Pre-generated ASIC synthesis results (ASAP7 7nm, 2.5 GHz) for a scaled configuration<br>- Synthesis scripts for regeneration (requires Synopsys Design Compiler)<br>- QEMU VM image with all dependencies pre-installed for easy evaluation<br>- Memory dump test data from standard benchmarks</p> <p>See the included README.md for setup and usage instructions.</p> |
| format | Recurso digital |
| id | zenodo_https___doi_org_10_5281_zenodo_19493662 |
| institution | Zenodo |
| language | eng |
| publishDate | 2026 |
| publisher | Zenodo |
| record_format | zenodo |
| spellingShingle | RST: Random-Access Hardware Sequence Compression — Artifact Chu, Nolan Lee, Yoon Panwar, Gagandeep Jian, Xun memory compression hardware acceleration DRAM sequence compression ASIC SystemVerilog computer architecture ISCA <p>Artifact for "Random-Access Hardware Sequence Compression" (ISCA 2026).</p> <p>This artifact contains:<br>- Software RST compression implementation (C++) for reproducing compression ratio results (Fig. 18, Fig. 19)<br>- SystemVerilog RTL for the RST compressor and decompressor, compilable with Verilator for functional verification and performance metric extraction<br>- Pre-generated ASIC synthesis results (ASAP7 7nm, 2.5 GHz) for a scaled configuration<br>- Synthesis scripts for regeneration (requires Synopsys Design Compiler)<br>- QEMU VM image with all dependencies pre-installed for easy evaluation<br>- Memory dump test data from standard benchmarks</p> <p>See the included README.md for setup and usage instructions.</p> |
| title | RST: Random-Access Hardware Sequence Compression — Artifact |
| topic | memory compression hardware acceleration DRAM sequence compression ASIC SystemVerilog computer architecture ISCA |
| url | https://doi.org/10.5281/zenodo.19493662 |