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| Main Authors: | , |
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| Format: | Recurso digital |
| Language: | English |
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Zenodo
2026
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| Online Access: | https://doi.org/10.5281/zenodo.20129234 |
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| _version_ | 1866901702393724928 |
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| author | Dorrer, Simon Pretl, Harald |
| author_facet | Dorrer, Simon Pretl, Harald |
| contents | <p>This Makefile-driven repository simulates, builds, and fully verifies (LVS, DRC, PEX) a complete analog mixed-signal chip for the ihp-sg13g2 130nm Open-PDK, including padframe generation and top-level assembly. It uses:</p> <ul> <li><strong>LibreLane</strong> for digital macro hardening, padframe generation and top-level assembly</li> <li><strong>Xschem</strong> for schematic entry</li> <li><strong>Ngspice</strong>, <strong>VACASK</strong> and <strong>CACE</strong> for analog simulation</li> <li><strong>KLayout</strong> for viewing and routing of the layout</li> <li><strong>Magic + Netgen</strong> and <strong>KLayout</strong> for LVS, DRC and PEX verification</li> <li><strong>SystemVerilog</strong>, <strong>cocotb</strong>, <strong>GTKWave</strong> and <strong>Surfer</strong> for digital simulation</li> </ul> <p>The repository is the starting point for your own custom silicon and provides a universal design flow solution: Just clone the repo, enter the IIC-OSIC-TOOLS container, and run <code>make all</code> to get a tapeout-ready analog-mixed signal chip. Focus on your design and do not care about the tools and the design flow!</p> <p>A step-by-step tutorial, including additional exercises, makes it easier to get started and is hosted with GitHub Pages.</p> |
| format | Recurso digital |
| id | zenodo_https___doi_org_10_5281_zenodo_20129234 |
| institution | Zenodo |
| language | eng |
| publishDate | 2026 |
| publisher | Zenodo |
| record_format | zenodo |
| spellingShingle | GitHub Repository of an Open-Source Analog-Mixed Signal Chip Design Template for the ihp-sg13g2 Open-PDK Dorrer, Simon Pretl, Harald <p>This Makefile-driven repository simulates, builds, and fully verifies (LVS, DRC, PEX) a complete analog mixed-signal chip for the ihp-sg13g2 130nm Open-PDK, including padframe generation and top-level assembly. It uses:</p> <ul> <li><strong>LibreLane</strong> for digital macro hardening, padframe generation and top-level assembly</li> <li><strong>Xschem</strong> for schematic entry</li> <li><strong>Ngspice</strong>, <strong>VACASK</strong> and <strong>CACE</strong> for analog simulation</li> <li><strong>KLayout</strong> for viewing and routing of the layout</li> <li><strong>Magic + Netgen</strong> and <strong>KLayout</strong> for LVS, DRC and PEX verification</li> <li><strong>SystemVerilog</strong>, <strong>cocotb</strong>, <strong>GTKWave</strong> and <strong>Surfer</strong> for digital simulation</li> </ul> <p>The repository is the starting point for your own custom silicon and provides a universal design flow solution: Just clone the repo, enter the IIC-OSIC-TOOLS container, and run <code>make all</code> to get a tapeout-ready analog-mixed signal chip. Focus on your design and do not care about the tools and the design flow!</p> <p>A step-by-step tutorial, including additional exercises, makes it easier to get started and is hosted with GitHub Pages.</p> |
| title | GitHub Repository of an Open-Source Analog-Mixed Signal Chip Design Template for the ihp-sg13g2 Open-PDK |
| url | https://doi.org/10.5281/zenodo.20129234 |