Salvato in:
| Autori principali: | , |
|---|---|
| Natura: | Recurso digital |
| Lingua: | inglese |
| Pubblicazione: |
Zenodo
2026
|
| Accesso online: | https://doi.org/10.5281/zenodo.20129234 |
| Tags: |
Aggiungi Tag
Nessun Tag, puoi essere il primo ad aggiungerne!!
|
Sommario:
- <p>This Makefile-driven repository simulates, builds, and fully verifies (LVS, DRC, PEX) a complete analog mixed-signal chip for the ihp-sg13g2 130nm Open-PDK, including padframe generation and top-level assembly. It uses:</p> <ul> <li><strong>LibreLane</strong> for digital macro hardening, padframe generation and top-level assembly</li> <li><strong>Xschem</strong> for schematic entry</li> <li><strong>Ngspice</strong>, <strong>VACASK</strong> and <strong>CACE</strong> for analog simulation</li> <li><strong>KLayout</strong> for viewing and routing of the layout</li> <li><strong>Magic + Netgen</strong> and <strong>KLayout</strong> for LVS, DRC and PEX verification</li> <li><strong>SystemVerilog</strong>, <strong>cocotb</strong>, <strong>GTKWave</strong> and <strong>Surfer</strong> for digital simulation</li> </ul> <p>The repository is the starting point for your own custom silicon and provides a universal design flow solution: Just clone the repo, enter the IIC-OSIC-TOOLS container, and run <code>make all</code> to get a tapeout-ready analog-mixed signal chip. Focus on your design and do not care about the tools and the design flow!</p> <p>A step-by-step tutorial, including additional exercises, makes it easier to get started and is hosted with GitHub Pages.</p>