| _version_ | 1866902307651715072 |
|---|---|
| author | Peng, Haipeng |
| author_facet | Peng, Haipeng |
| contents | <p>One-time secure chips are a critical component of hardware roots of<br>trust, but existing schemes only support simple counting and cannot ex<br>press complex dependencies (e.g., “A and (B or C)”), nor do they offer<br>publicly verifiable consumption records. This paper proposes a one-time<br>secure chip design based on Multiplicative Linear Logic (MLL) proof nets.<br>We compile arbitrary Boolean expressions or partial orders into a Logic<br>Net—a graph representation derived from MLL proof nets by promoting<br>cut edges to nodes—satisfying the Danos-R´egnier correctness condition,<br>and then statically map it to an on-chip One-Time Programmable (OTP)<br>array and combinational logic condition gates. The cut elimination opera<br>tion in proof nets is atomically mapped to the blowing of specific OTP bits,<br>and the elimination condition for each cut is enforced by hardware combi<br>national logic. We formally define an ideal hardware model and adversary<br>capabilities, and prove three core security properties—one-time, depen<br>dency enforcement (for AND dependencies), and public auditability—in<br>the information-theoretic sense. Cloning resistance is achieved via a phys<br>ically unclonable function (PUF) challenge-response under the ideal PUF<br>model (information-theoretic) or via digital signatures (computational).<br>We develop a Python simulator that models fixed condition circuits, and<br>validate the scheme in realistic scenarios (bank dual authorization, mis<br>sile dual-token launch, high-stakes exam decryption) as well as a complex<br>AND/ORtest. Finally, we discuss the hardware feasibility of the proposed<br>design and outline future implementation directions. This work provides<br>a complete theoretical framework, a reproducible simulation tool, and a<br>clear path toward programmable, verifiable one-time hardware security.<br>Keywords: One-timesecure chip; proof net; cut elimination; information</p> |
| format | Recurso digital |
| id | zenodo_https___doi_org_10_5281_zenodo_20177865 |
| institution | Zenodo |
| language | |
| publishDate | 2026 |
| publisher | Zenodo |
| record_format | zenodo |
| spellingShingle | One-Time Secure Chip Peng, Haipeng <p>One-time secure chips are a critical component of hardware roots of<br>trust, but existing schemes only support simple counting and cannot ex<br>press complex dependencies (e.g., “A and (B or C)”), nor do they offer<br>publicly verifiable consumption records. This paper proposes a one-time<br>secure chip design based on Multiplicative Linear Logic (MLL) proof nets.<br>We compile arbitrary Boolean expressions or partial orders into a Logic<br>Net—a graph representation derived from MLL proof nets by promoting<br>cut edges to nodes—satisfying the Danos-R´egnier correctness condition,<br>and then statically map it to an on-chip One-Time Programmable (OTP)<br>array and combinational logic condition gates. The cut elimination opera<br>tion in proof nets is atomically mapped to the blowing of specific OTP bits,<br>and the elimination condition for each cut is enforced by hardware combi<br>national logic. We formally define an ideal hardware model and adversary<br>capabilities, and prove three core security properties—one-time, depen<br>dency enforcement (for AND dependencies), and public auditability—in<br>the information-theoretic sense. Cloning resistance is achieved via a phys<br>ically unclonable function (PUF) challenge-response under the ideal PUF<br>model (information-theoretic) or via digital signatures (computational).<br>We develop a Python simulator that models fixed condition circuits, and<br>validate the scheme in realistic scenarios (bank dual authorization, mis<br>sile dual-token launch, high-stakes exam decryption) as well as a complex<br>AND/ORtest. Finally, we discuss the hardware feasibility of the proposed<br>design and outline future implementation directions. This work provides<br>a complete theoretical framework, a reproducible simulation tool, and a<br>clear path toward programmable, verifiable one-time hardware security.<br>Keywords: One-timesecure chip; proof net; cut elimination; information</p> |
| title | One-Time Secure Chip |
| url | https://doi.org/10.5281/zenodo.20177865 |