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| Main Authors: | , , , , , |
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| Format: | Recurso digital |
| Language: | |
| Published: |
Zenodo
2026
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| Online Access: | https://doi.org/10.5281/zenodo.20392647 |
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Table of Contents:
- <p>We are entering a new age, and with it comes a surge in interest in generative AI and machine learning throughout the world. As computing talents start to reveal their true colors, there is a pressing demand for efficient and fast microprocessors. The RISC design approach, which stresses a smaller and simpler set of instructions, each executed in a constant amount of time, is widely used by current processors to achieve improved efficiency. A five-stage pipelined general-purpose microprocessor architecture with a clock period of 0.59 nanoseconds has been the target of this study, which translates to optimization approaches being implemented in Verilog code. In addition, by switching to True Single- Phase Clocking (TSPC) flip-flops, we may cut power usage by 20% and cut the number of transistors used by half. The use of Verilog HDL on ModelSim and Xilinx to achieve an n-stage pipelined architecture for a general-purpose microprocessor is shown in this work as an example of RISC-V embedded processor design.</p>