Gajaria, D., & Adegbija, T. (2024). ARC: DVFS-Aware Asymmetric-Retention STT-RAM Caches for Energy-Efficient Multicore Processors.
Cita Chicago Style (17a ed.)Gajaria, Dhruv, y Tosiron Adegbija. ARC: DVFS-Aware Asymmetric-Retention STT-RAM Caches for Energy-Efficient Multicore Processors. 2024.
Cita MLA (9a ed.)Gajaria, Dhruv, y Tosiron Adegbija. ARC: DVFS-Aware Asymmetric-Retention STT-RAM Caches for Energy-Efficient Multicore Processors. 2024.
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