APA (7th ed.) Citation

Hokenmaier, W., Jurasek, R., Bowen, E., Granger, R., & Odom, D. (2024). Co-design of a novel CMOS highly parallel, low-power, multi-chip neural network accelerator.

Chicago Style (17th ed.) Citation

Hokenmaier, W., R. Jurasek, E. Bowen, R. Granger, and D. Odom. Co-design of a Novel CMOS Highly Parallel, Low-power, Multi-chip Neural Network Accelerator. 2024.

MLA (9th ed.) Citation

Hokenmaier, W., et al. Co-design of a Novel CMOS Highly Parallel, Low-power, Multi-chip Neural Network Accelerator. 2024.