Hokenmaier, W., Jurasek, R., Bowen, E., Granger, R., & Odom, D. (2024). Co-design of a novel CMOS highly parallel, low-power, multi-chip neural network accelerator.
Style de citation Chicago (17e éd.)Hokenmaier, W., R. Jurasek, E. Bowen, R. Granger, et D. Odom. Co-design of a Novel CMOS Highly Parallel, Low-power, Multi-chip Neural Network Accelerator. 2024.
Style de citation MLA (9e éd.)Hokenmaier, W., et al. Co-design of a Novel CMOS Highly Parallel, Low-power, Multi-chip Neural Network Accelerator. 2024.
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