:: Library Catalog

Cover Image

Saved in:

Bibliographic Details
Main Authors:	Ray, Yudhajit, Ghosh, Archisman, Sen, Shreyas
Format:	Preprint
Published:	2024
Subjects:	Signal Processing Hardware Architecture
Online Access:	https://arxiv.org/abs/2410.16310
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

Toward designing workload-aware Surface Code Architectures
by: Ghosh, Archisman, et al.
Published: (2026)

No Tile Left Behind: Multiprogramming for Surface-Code Architectures
by: Ghosh, Archisman, et al.
Published: (2026)

Survival of the Optimized: An Evolutionary Approach to T-depth Reduction
by: Ghosh, Archisman, et al.
Published: (2025)

A 950 MHz SIMT Soft Processor
by: Langhammer, Martin, et al.
Published: (2025)

Enhanced Hybrid Temporal Computing Using Deterministic Summations for Ultra-Low-Power Accelerators
by: Sachdeva, Sachin, et al.
Published: (2025)

Ultra8T: A Sub-Threshold 8T SRAM with Leakage Detection
by: Shen, Shan, et al.
Published: (2023)

Guardians of the Quantum GAN
by: Ghosh, Archisman, et al.
Published: (2024)

M100: An Orchestrated Dataflow Architecture Powering General AI Computing
by: Xie, Yan, et al.
Published: (2026)

Switch-Less Dragonfly on Wafers: A Scalable Interconnection Architecture based on Wafer-Scale Integration
by: Feng, Yinxiao, et al.
Published: (2024)

SPARQLe: Sub-Precision Activation Representation for Quantized LLM Inference
by: Parvathy, Aradhana Mohan, et al.
Published: (2026)

HCiM: ADC-Less Hybrid Analog-Digital Compute in Memory Accelerator for Deep Learning Workloads
by: Negi, Shubham, et al.
Published: (2024)

Transimpedance Amplifier with Automatic Gain Control Based on Memristors for Optical Signal Acquisition
by: Hodisan, Sariel, et al.
Published: (2024)

Design and Performance Analysis of an Ultra-Low Power Integrate-and-Fire Neuron Circuit Using Nanoscale Side-contacted Field Effect Diode Technology
by: Motaman, Seyedmohamadjavad, et al.
Published: (2024)

COmPOSER: Circuit Optimization of mm-wave/RF circuits with Performance-Oriented Synthesis for Efficient Realizations
by: Ghosh, Subhadip, et al.
Published: (2026)

Ultra Low-Power SDM-based Circuit-Switching for Networks-on-Chip
by: Zaeemi, Meysam, et al.
Published: (2026)

A Reconfigurable Computing In-Memory Macro with Charge-sharing-based Weighted Accumulator
by: Yang, Junyi, et al.
Published: (2026)

Empirically-Calibrated H100 Node Power Models for Reducing Uncertainty in AI Training Energy Estimation
by: Newkirk, Alex C., et al.
Published: (2025)

Latch Based Design for Fast Voltage Droop Response
by: Srinivas, Shreyas, et al.
Published: (2025)

SparseDPD: A Sparse Neural Network-based Digital Predistortion FPGA Accelerator for RF Power Amplifier Linearization
by: Versluis, Manno, et al.
Published: (2025)

RFAmpDesigner: A Self-Evolving Multi-Agent LLM Framework for Automated Radio Frequency Amplifier Design
by: Lu, Hang, et al.
Published: (2026)

MXFormer: A Microscaling Floating-Point Charge-Trap Transistor Compute-in-Memory Transformer Accelerator
by: Karfakis, George, et al.
Published: (2026)

HULK-V: a Heterogeneous Ultra-low-power Linux capable RISC-V SoC
by: Valente, Luca, et al.
Published: (2022)

PELS: A Lightweight and Flexible Peripheral Event Linking System for Ultra-Low Power IoT Processors
by: Ottaviano, Alessandro, et al.
Published: (2023)

X-HEEP: An Open-Source, Configurable and Extendible RISC-V Microcontroller for the Exploration of Ultra-Low-Power Edge Accelerators
by: Machetti, Simone, et al.
Published: (2024)

Blink: Fast Automated Design of Run-Time Power Monitors on FPGA-Based Computing Platforms
by: Galimberti, Andrea, et al.
Published: (2024)

A Logic-Reuse Approach to Nibble-based Multiplier Design for Low Power Vector Computing
by: Chowdhury, Md Rownak Hossain, et al.
Published: (2026)

LIMCA: LLM for Automating Analog In-Memory Computing Architecture Design Exploration
by: Vungarala, Deepak, et al.
Published: (2025)

Benchmarking Ultra-Low-Power $μ$NPUs
by: Millar, Josh, et al.
Published: (2025)

SiTe CiM: Signed Ternary Computing-in-Memory for Ultra-Low Precision Deep Neural Networks
by: Thakuria, Niharika, et al.
Published: (2024)

A DSP shared is a DSP earned: HLS Task-Level Multi-Pumping for High-Performance Low-Resource Designs
by: Brignone, Giovanni, et al.
Published: (2023)

In-Pipeline Integration of Digital In-Memory-Computing into RISC-V Vector Architecture to Accelerate Deep Learning
by: Spagnolo, Tommaso, et al.
Published: (2026)

Small Logic-based Multipliers with Incomplete Sub-Multipliers for FPGAs
by: Böttcher, Andreas, et al.
Published: (2024)

A 0.96pJ/SOP, 30.23K-neuron/mm^2 Heterogeneous Neuromorphic Chip With Fullerene-like Interconnection Topology for Edge-AI Computing
by: Zhou, P. J., et al.
Published: (2024)

GEM3D CIM General Purpose Matrix Computation Using 3D Integrated SRAM eDRAM Hybrid Compute In Memory on Memory Architecture
by: Chakraborty, Subhradip, et al.
Published: (2026)

AraXL: A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors
by: Purayil, Navaneeth Kunhi, et al.
Published: (2025)

On the Excitability of Ultra-Low-Power CMOS Analog Spiking Neurons
by: Van Brandt, Léopold, et al.
Published: (2025)

AutoPower: Automated Few-Shot Architecture-Level Power Modeling by Power Group Decoupling
by: Zhang, Qijun, et al.
Published: (2025)

Neuromorphic Computing for Low-Power Artificial Intelligence
by: Katti, Keshava, et al.
Published: (2026)

DX100: A Programmable Data Access Accelerator for Indirection
by: Khadem, Alireza, et al.
Published: (2025)

An Analog and Digital Hybrid Attention Accelerator for Transformers with Charge-based In-memory Computing
by: Moradifirouzabadi, Ashkan, et al.
Published: (2024)