Saved in:
| Main Authors: | , , , , , , , , , , , , , , , |
|---|---|
| Format: | Preprint |
| Published: |
2024
|
| Subjects: | |
| Online Access: | https://arxiv.org/abs/2411.00309 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| _version_ | 1866912099881451520 |
|---|---|
| author | Wu, Heng Lu, Haoran Peng, Wanyue Xu, Ziqiao Chu, Yanbang Sun, Jiacheng Zhou, Falong Wu, Jack Zhang, Lijie Bu, Weihai Kang, Jin Li, Ming Lin, Yibo Wang, Runsheng Zhang, Xin Huang, Ru |
| author_facet | Wu, Heng Lu, Haoran Peng, Wanyue Xu, Ziqiao Chu, Yanbang Sun, Jiacheng Zhou, Falong Wu, Jack Zhang, Lijie Bu, Weihai Kang, Jin Li, Ming Lin, Yibo Wang, Runsheng Zhang, Xin Huang, Ru |
| contents | In this work, we proposed a new 3D integration technology: the Flip 3D integration (F3D), consisting of the 3D transistor stacking, the 3D dual-sided interconnects, the 3D die-to-die stacking and the dual-sided Monolithic 3D (M3D). Based on a 32-bit FFET RISCV core, besides the scaling benefits of the Flip FET (FFET), the dual-sided signal routing shows even more routing flexibility with 6.8% area reduction and 5.9% EDP improvement. Novel concepts of Multi-Flipping processes (Double Flips and Triple Flips) were proposed to relax the thermal budget constraints in the F3D and thus support the dual-sided M3D in the F3D. The core's EDP and frequency are improved by up to 3.2% and 2.3% respectively, after BEOL optimizations based on the Triple Flips compared with unoptimized ones. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2411_00309 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | From Flip FET to Flip 3D Integration (F3D): Maximizing the Scaling Potential of Wafer Both Sides Beyond Conventional 3D Integration Wu, Heng Lu, Haoran Peng, Wanyue Xu, Ziqiao Chu, Yanbang Sun, Jiacheng Zhou, Falong Wu, Jack Zhang, Lijie Bu, Weihai Kang, Jin Li, Ming Lin, Yibo Wang, Runsheng Zhang, Xin Huang, Ru Mesoscale and Nanoscale Physics In this work, we proposed a new 3D integration technology: the Flip 3D integration (F3D), consisting of the 3D transistor stacking, the 3D dual-sided interconnects, the 3D die-to-die stacking and the dual-sided Monolithic 3D (M3D). Based on a 32-bit FFET RISCV core, besides the scaling benefits of the Flip FET (FFET), the dual-sided signal routing shows even more routing flexibility with 6.8% area reduction and 5.9% EDP improvement. Novel concepts of Multi-Flipping processes (Double Flips and Triple Flips) were proposed to relax the thermal budget constraints in the F3D and thus support the dual-sided M3D in the F3D. The core's EDP and frequency are improved by up to 3.2% and 2.3% respectively, after BEOL optimizations based on the Triple Flips compared with unoptimized ones. |
| title | From Flip FET to Flip 3D Integration (F3D): Maximizing the Scaling Potential of Wafer Both Sides Beyond Conventional 3D Integration |
| topic | Mesoscale and Nanoscale Physics |
| url | https://arxiv.org/abs/2411.00309 |