APA-Zitierstil (7. Ausg.)

Liang, Z., Yan, X., Ning, Z., Hu, J., Jiang, X., Sun, Y., . . . Ye, J. (2024). A 64-Channel Precision Time-to-Digital Converter with Average 4.77 ps RMS Implemented in a 28 nm FPGA.

Chicago-Zitierstil (17. Ausg.)

Liang, Zehong, Xiongbo Yan, Zhe Ning, Jun Hu, Xiaoshan Jiang, Yunhua Sun, Weiyan Pan, und Jingbo Ye. A 64-Channel Precision Time-to-Digital Converter with Average 4.77 Ps RMS Implemented in a 28 Nm FPGA. 2024.

MLA-Zitierstil (9. Ausg.)

Liang, Zehong, et al. A 64-Channel Precision Time-to-Digital Converter with Average 4.77 Ps RMS Implemented in a 28 Nm FPGA. 2024.